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EPCQ128SI16N

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
Status Register Content Memory Content
TB Bit BP3 Bit BP2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area
1 0 1 0 1 Sectors (0 to 15) Sectors (16 to 1023)
1 0 1 1 0 Sectors (0 to 31) Sectors (32 to 1023)
1 0 1 1 1 Sectors (0 to 63) Sectors (64 to 1023)
1 1 0 0 0 Sectors (0 to 127) Sectors (128 to 1023)
1 1 0 0 1 Sectors (0 to 255) Sectors (256 to 1023)
1 1 0 1 0 Sectors (0 to 511) Sectors (512 to 1023)
1 1 0 1 1 All sectors None
1 1 1 0 0 All sectors None
1 1 1 0 1 All sectors None
1 1 1 1 0 All sectors None
1 1 1 1 1 All sectors None
1.6.1.2. Write Status Register Operation (01h)
The write status operation does not affect the write enable latch and write in progress
bits. You can use the write status operation to set the status register block protection
and top or bottom bits. Therefore, you can implement this operation to protect certain
memory sectors. After setting the block protect bits, the protected memory sectors
are treated as read-only memory. You must execute the write enable operation before
the write status operation.
Figure 2. Write Status Operation Timing Diagram
Operation Code (01h) Status Register
DATA0
nCS
DCLK
DATA
High Impedance
0
1
2
3
4
5
6
7
8 9 10 11 12 13 14 15
0
1
2
3
4
5
6
7
MSB
Immediately after the nCS signal drives high, the device initiates the self-timed write
status cycle. The self-timed write status cycle usually takes 5 ms for all EPCQ devices
and is guaranteed to be less than 8 ms. For details about t
WS
, refer to the related
information below. You must account for this delay to ensure that the status register is
written with the desired block protect bits. Alternatively, you can check the write in
progress bit in the status register by executing the read status operation while the
self-timed write status cycle is in progress. Set the write in progress bit to 1 during
the self-timed write status cycle and 0 when it is complete.
Related Information
Write Operation Timing on page 40
The Write Operation Parameters provides more information about t
WS
, t
ES
and t
WB
.
1. Quad-Serial Configuration (EPCQ) Devices Datasheet
CF52012 | 2018.06.01
Quad-Serial Configuration (EPCQ) Devices Datasheet
25
1.6.2. Flag Status Register
Table 27. Flag Status Register Bits
Bit Name Value Description
7 Write or Erase
Controller
(11)
• 1=Ready
• 0=Busy
Indicates whether one of the following operation is in
progress:
• Write Status Register
• Write NVCR
• Write Bytes
• Erase
6 Erase suspend • 1=In effect
• 0=Not in effect
Indicates whether an Erase operation has been or is going
to be suspended.
Note: Status bits are reset automatically
5 Erase • 1=Failure or protection
error
• 0=Clear
Indicates whether an Erase operation has succeeded or
failed.
4 Write • 1=Failure or protection
error
• 0=Clear
Indicates whether a Write Bytes operation has succeeded or
failed; also an attempt to write a 0 to a 1 when VPP = VPPH
and the data pattern is a multiple of 64 bits.
3 Reserved
2 Write suspend • 1=In effect
• 0=Not in effect
Indicates whether a Write Bytes operation has been or will
be suspended.
1 Protection • 1=Failure or protection
error
• 0=Clear
Indicates whether an Erase or Write Bytes operation has
attempted to modify the protected array sector.
0 Addressing • 1=4-bytes addressing
• 0=3-bytes addressing
Indicates the addressing mode used.
1.6.2.1. Read Flag Status Register Operation(70h)
The Read flag status register can be read continuously and at any time, including
during a write or erase operation. You must read the Read flag status register every
time a write or erase command is issued.
Figure 3. Read Flag Status Register Operation Timing Diagram
nCS
DCLK
DATA0
DATA
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
7 6 5 4 3 2 1 0 7 2 1 0 76 5 4 3
Operation Code (70h)
MSB MSB
Status Register Out Status Register Out
High Impedance
(11)
Write or erase controller bit = NOT write in progress bit.
1. Quad-Serial Configuration (EPCQ) Devices Datasheet
CF52012 | 2018.06.01
Quad-Serial Configuration (EPCQ) Devices Datasheet
26
1.6.3. Non-Volatile Configuration Register
Table 28. Dummy Clock Cycles and Address Bytes for the Non-Volatile Configuration
Register Operation
FPGA Device Dummy Clock Cycles
AS x1 AS x4
• Arria
®
GX
• Arria II
• Cyclone
®
• Cyclone II
• Cyclone III
• Cyclone IV
• Stratix
®
• Stratix GX
• Stratix II
• Stratix II GX
• Stratix III
• Stratix IV
• Intel Cyclone 10 LP
8 —
Table 29. Dummy Clock Cycles and Address Bytes for the Non-Volatile Configuration
Register Operation for Arria V, Cyclone V and Stratix V Devices
FPGA Device Address Bytes
(12)
Dummy Clock Cycles
AS x1 AS x4
• Arria V
• Cyclone V
• Stratix V
3-byte addressing 12 12
4-byte addressing 4 10
Table 30. Non-Volatile Configuration Register Operation Bit Definition
Bit Description Default Value
15:12 Number of dummy clock cycles. When this number is from 0001 to 1110, the
dummy clock cycles is from 1 to 14.
0000 or 1111
(13)
11:5
Set these bits to 1111111. 1111111
4 Don't care.
1
3:1
Set these bits to 111. 111
0 Address byte setting.
•
0—4-byte addressing
•
1—3-byte addressing
1
(12)
The 4-byte addressing mode is used for EPCQ256 and EPCQ512/A devices.
(13)
The default dummy clock cycles is 10 for extended quad input fast read and 8 for extended
dual input fast and standard fast read.
1. Quad-Serial Configuration (EPCQ) Devices Datasheet
CF52012 | 2018.06.01
Quad-Serial Configuration (EPCQ) Devices Datasheet
27
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

EPCQ128SI16N

Mfr. #:
Buy EPCQ128SI16N
Manufacturer:
Intel / Altera
Description:
FPGA - Configuration Memory IC - Ser. Config Mem Flash 128Mb 50 MHz
Lifecycle:
New from this manufacturer.
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