1.6.3.1. Read Non-Volatile Configuration Register Operation (B5h)
To execute a read non-volatile configuration register, drive the nCS low. For extended
SPI protocol, the operation code is input on DATA0, and output on DATA1. You can
terminate the operation by driving the nCS low at any time during data output. The
nonvolatile configuration register can be read continuously. After all 16 bits of the
register have been read, a 0 is output.
Figure 4. Read Non-Volatile Configuration Register Operation Timing Diagram
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Operation Code (B5h)
High Impedance
NVCR Out NVCR Out
LS Byte MS Byte
nCS
DCLK
DATA0
DATA
1.6.3.2. Write Non-Volatile Configuration Register Operation (B1h)
You need to write the non-volatile configuration registers for EPCQ devices for
different configuration schemes. If you are using the .jic file, the Intel Quartus Prime
programmer sets the number of dummy clock cycles and address bytes accordingly. If
you are using an external programmer tools, you must set the non-volatile
configuration registers.
To set the non-volatile configuration register, follow these steps:
1. Execute the write enable operation.
2. Execute the write non-volatile configuration register operation.
3. Set the 16-bit register value.
Set the 16-bit register value as b'1110 111y xxxx 1111 where y is the address
byte (0 for 4-byte addressing and 1 for 3-byte addressing) and xxxx is the dummy
clock value. When the xxxx value is from 0001 to 1110, the dummy clock value is
from 1 to 14. When xxxx is 0000 or 1111, the dummy clock value is at the default
value, which is 8 for standard fast read (AS x1) mode and 10 for extended quad input
fast read (AS x4 mode).
1. Quad-Serial Configuration (EPCQ) Devices Datasheet
CF52012 | 2018.06.01
Quad-Serial Configuration (EPCQ) Devices Datasheet
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