© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 3
1 Publication Order Number:
NTMD6N02R2/D
NTMD6N02R2
Power MOSFET
6.0 Amps, 20 Volts
N−Channel Enhancement Mode
Dual SO−8 Package
Features
• Ultra Low R
DS(on)
• Higher Efficiency Extending Battery Life
• Logic Level Gate Drive
• Miniature Dual SOIC−8 Surface Mount Package
• Diode Exhibits High Speed, Soft Recovery
• Avalanche Energy Specified
• SOIC−8 Mounting Information Provided
• Pb−Free Package is Available
Applications
• DC−DC Converters
• Low Voltage Motor Control
• Power Management in Portable and Battery−Powered Products,
for example, Computers, Printers, Cellular and Cordless Telephones
and PCMCIA Cards
MAXIMUM RATINGS (T
J
= 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain−to−Source Voltage V
DSS
20 V
Drain−to−Gate Voltage (R
GS
= 1.0 MW)
V
DGR
20 V
Gate−to−Source Voltage − Continuous V
GS
"12 V
Thermal Resistance,
Junction−to−Ambient (Note 1)
Total Power Dissipation @ T
A
= 25°C
Continuous Drain Current @ T
A
= 25°C
Continuous Drain Current @ T
A
= 70°C
Pulsed Drain Current (Note 4)
R
q
JA
P
D
I
D
I
D
I
DM
62.5
2.0
6.5
5.5
50
°C/W
W
A
A
A
Thermal Resistance,
Junction−to−Ambient (Note 2)
Total Power Dissipation @ T
A
= 25°C
Continuous Drain Current @ T
A
= 25°C
Continuous Drain Current @ T
A
= 70°C
Pulsed Drain Current (Note 4)
R
q
JA
P
D
I
D
I
D
I
DM
102
1.22
5.07
4.07
40
°C/W
W
A
A
A
Thermal Resistance
Junction−to−Ambient (Note 3)
Total Power Dissipation @ T
A
= 25°C
Continuous Drain Current @ T
A
= 25°C
Continuous Drain Current @ T
A
= 70°C
Pulsed Drain Current (Note 4)
R
q
JA
P
D
I
D
I
D
I
DM
172
0.73
3.92
3.14
30
°C/W
W
A
A
A
1. Mounted onto a 2 in square FR−4 Board
(1 in sq. 2 oz. Cu 0.06 in thick single sided), t < 10 seconds.
2. Mounted onto a 2 in square FR−4 Board
(1 in sq. 2 oz. Cu 0.06 in thick single sided), t = steady state.
3. Minimum FR−4 or G−10 PCB, t = steady state.
4. Pulse Test: Pulse Width = 10 ms, Duty Cycle = 2%.
Device Package Shipping
†
ORDERING INFORMATION
NTMD6N02R2 SOIC−8 2500/Tape & Reel
N−Channel
D
S
G
MARKING DIAGRAM
& PIN ASSIGNMENT
Source 1
Gate 1
Source 2
Gate 2
Drain 1
Drain 1
Drain 2
Drain 2
(Top View)
2
3
4
1
7
6
5
8
http://onsemi.com
V
DSS
R
DS(ON)
TYP I
D
MAX
20 V
35 mW @ V
GS
= 4.5 V
6.0 A
SOIC−8
CASE 751
STYLE 11
1
8
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
NTMD6N02R2G SOIC−8
(Pb−Free)
2500/Tape & Reel
E6N02
ALYWG
G
E6N02 = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location
