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8N3S271EC-0158CDI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
DATA SHEET
IDT8N3S271CCD
REVISION A DECEMBER 17, 2012
1 ©2012 Integrated Device Technology, Inc.
LVPECL Frequency-Programmable
Crystal Oscillator
IDT8N3S271
General Description
The IDT8N3S271 is a Frequency-Programmable Crystal Oscillator
with very flexible frequency programming capabilities. The device
uses IDT’s fourth generation FemtoClock® NG technology for an
optimum of high clock frequency and low phase noise performance.
The device accepts 2.5V or 3.3V supply and is packaged in a small,
lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm package.
The device can be factory programmed to any frequency in the range
from 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz and
supports a very high degree of frequency precision of 218Hz or
better. The extended temperature range supports wireless
infrastructure, telecommunication and networking end equipment
requirements.
Features
• Fourth generation FemtoClock® NG technology
• Factory-programmable clock output frequency from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz
• Frequency programming resolution is 218Hz and better
• One 2.5V or 3.3V LVPECL clock output
• Output enable control (positive polarity), LVCMOS/LVTTL
compatible
• RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.24ps
(typical), integer PLL feedback configuration
• RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.27ps (typical),
integer PLL feedback configuration
• 2.5V or 3.3V supply
• -40°C to 85°C ambient operating temperature
• Available in a lead-free (RoHS 6) 6-pin ceramic package
1
2
3
6
5
4
DNU
OE
V
EE
V
CC
nQ
Q
IDT8N3S271
6-lead ceramic 5mm x 7mm x 1.55mm
package body
CD Package
Top View
Pin Assignment
Block Diagram
Q
nQ
OSC
f
XTAL
÷MINT, MFRAC
PFD
&
LPF
FemtoClock® NG
VCO
1950-2600MHz
÷N
Configuration Register (ROM)
25
7
OE
Pullup
2
÷P
IDT8N3S271 Data Sheet LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
IDT8N3S271CCD
REVISION A DECEMBER 17, 2012
2 ©2012 Integrated Device Technology, Inc.
Pin Description and Characteristic Tables
NOTE: Pullup refers to internal input resistor. See Table 2, Pin Characteristics, for typical values.
Function Tables
Table 3A. OE Configuration
Output EnableOE
0 Outputs Q, nQ are in hi
gh-impedance state.
1 (default) Outputs are enabled.
NOTE: OE is an asynchronous control.
NO
TE: Supported output frequency range. The output frequency can be programmed to any frequency in this range and to a precision of
218Hz or better.
Table 1. Pin Descriptions
Number Name Type Description
1DNU
Do not use (factory use only).
2 OE Input Pullup
Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface levels.
3V
EE
Power Negative power supply.
4, 5
Q, nQ
Output Differential clock output. LVPECL interface levels.
6
V
CC
Power Positive power supply.
Table 2. Pin Characteristics
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance OE 5.5 pF
R
PULLUP
Input Pullup Resistor 50 k
Input
Table 3B. Output Frequency Range
15.476MHz to 866.67MHz
975MHz to 1,300MHz
IDT8N3S271 Data Sheet LVPECL FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR
IDT8N3S271CCD
REVISION A DECEMBER 17, 2012
3 ©2012 Integrated Device Technology, Inc.
Principles of Operation
The block diagram consists of the internal 3rd overtone crystal and
oscillator which provide the reference clock f
XTAL
of either
114.285MHz or 100MHz. The PLL includes the FemtoClock NG VCO
along with the Pre-divider (P), the feedback divider (M) and the post
divider (N). The P, M, and N dividers determine the output frequency
based on the f
XTAL
reference. The feedback divider is fractional
supporting a huge number of output frequencies. The configuration
of the feedback divider to integer-only values results in an improved
output phase noise characteristics at the expense of the range of
output frequencies. Internal registers are used to hold one factory
pre-set P, M, and N configuration setting. The P, M, and N frequency
configuration supports an output frequency range from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz.
The devices use the fractional feedback divider with a delta-sigma
modul
ator for noise shaping and robust frequency synthesis
capability. The relatively high reference frequency minimizes phase
noise generated by frequency multiplication and allows more efficient
shaping of noise by the delta-sigma modulator.
The output frequency is determine
d by the 2-bit pre-divider (P), the
feedback divider (M) and the 7-bit post divider (N). The feedback
divider (M) consists of both a 7-bit integer portion (MINT) and an
18-bit fractional portion (MFRAC) and provides the means for
high-resolution frequency generation. The output frequency f
OUT
is
calculated by:
f
OUT
f
XTAL
1
PN
------------
MINT
MFRAC 0.5+
2
18
-------------------------------------+=
Frequency Configuration
An order code is assigned to each frequency configuration
programmed by the factory (default frequencies). For more
information on the available default frequencies and order codes,
please see the Ordering Information section in this document. For
available order codes, see the FemtoClock NG Ceramic-Package XO
and VCXO Ordering Product Information document.
For more information on programming capabilities of the device for
custom frequency and pull-range configurations, see the FemtoClock
NG Ceramic 5x7 Module Programming Guide.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

8N3S271EC-0158CDI

Mfr. #:
Buy 8N3S271EC-0158CDI
Manufacturer:
IDT
Description:
Programmable Oscillators PROGRAMMABLE FEMTOCLOCK
Lifecycle:
New from this manufacturer.
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