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MAX13172ECAI+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
MAX13172E
+5V Multiprotocol, Software-Selectable
Clock Transceiver
10 ______________________________________________________________________________________
+1V
-1V
V
0H
V
0L
A -B
R
0
INPUT
OUTPUT
0
t
PLH
t
PHL
f = 1MHz: t
r
, t
f
≤ 1ns
V
CC
/2
V
CC
/2
90%
10%
t
R
90%
10%
t
F
0
t
PHL
0
V
0H
-V
0L
TIN_
A
10%
90%
tF
0
t
PLH
90%
10%
t
R
t
R
, t
F
≤ 10ns
V
CC
/2 V
CC
/2
V
CC
Figure 6. V.11 Receiver Propagation Delays
Figure 7. V.10 Transmitter Propagation Delays
V
IH
V
IL
V
0H
V
0L
A
R
0
t
PHL
0
t
PLH
t
R
, t
F
≤ 10ns
V
CC
/2
V
CC
/2
90%
10%
t
F
90%
10%
t
R
Figure 8. V.10 Receiver Propogation Delays
V
CC
/2
90%
10%
50%
t
PLH
V
CC
0
V
0
-V
0
TIN_
A - B
t
R
V
CC
/2
t
PHL
90%
10%
50%
t
F
f = 1MHz: t
r
, t
f
≤ 1ns
Figure 5. V.11 Transmitter Propogation Delays
Switching Time Waveforms
MAX13172E
PROTOCOL M2 M1 M0
DCE/
DTE
INVERT T1 T2 T3 R1 R2 R3 T4 R4
Not Used
(Default V.11)
0 0 0 0 0 V.11 V.11 Z V.11 V.11 V.11 Z V.10
RS-530A 0 0 1 0 0 V.11 V.10 Z V.11 V.10 V.11 Z V.10
RS-530 0 1 0 0 0 V.11 V.11 Z V.11 V.11 V.11 Z V.10
X.21 0 1 1 0 0 V.11 V.11 Z V.11 V.11 V.11 Z V.10
V.35 1 0 0 0 0 V.28 V.28 Z V.28 V.28 V.28 Z V.28
RS-449/V.36 1 0 1 0 0 V.11 V.11 Z V.11 V.11 V.11 Z V.10
V.28/RS-232 1 1 0 0 0 V.28 V.28 Z V.28 V.28 V.28 Z V.28
No Cable 1 1 1 0 0 Z Z Z Z Z Z Z Z
Not Used
(Default V.11)
0 0 0 0 1 V.11 V.11 Z V.11 V.11 V.11 V.10 Z
RS-530A 0 0 1 0 1 V.11 V.10 Z V.11 V.10 V.11 V.10 Z
RS-530 0 1 0 0 1 V.11 V.11 Z V.11 V.11 V.11 V.10 Z
X.21 0 1 1 0 1 V.11 V.11 Z V.11 V.11 V.11 V.10 Z
V.35 1 0 0 0 1 V.28 V.28 Z V.28 V.28 V.28 V.28 Z
RS-449/V.36 1 0 1 0 1 V.11 V.11 Z V.11 V.11 V.11 V.10 Z
V.28/RS-232 1 1 0 0 1 V.28 V.28 Z V.28 V.28 V.28 V.28 Z
No Cable 1 1 1 0 1 Z Z Z Z Z Z Z Z
Table 1. Mode Select Table
+5V Multiprotocol, Software-Selectable
Clock Transceiver
______________________________________________________________________________________ 11
V
IH
V
IL
(2.0V)
(-0.3V)
V
0H
V
0L
A
R
1.3V
t
PHL
1.3V
t
PLH
t
R
, t
F
≤ 10ns
V
CC
/2
V
CC
/2
90%
10%
t
F
90%
10%
t
R
Figure 10. V.28 Receiver Propogation Delays
Switching Time Waveforms (continued)
0
t
PHL
0
V
0H
-V
0L
TIN_
A
-3V
3V
tF
SR
F
= 6/t
F
SR
R
= 6/t
R
0
t
PLH
3V
-3V
t
R
t
R
, t
F
≤ 10ns
V
CC
/2 V
CC
/2
V
CC
Figure 9. V.28 Transmitter Propagation Delays
MAX13172E
+5V Multiprotocol, Software-Selectable
Clock Transceiver
12 ______________________________________________________________________________________
The MAX13172E’s mode can be selected through soft-
ware control of the M0, M1, M2, INVERT, and DCE/DTE
inputs. Alternatively, the mode can be selected by
shorting the appropriate combination of mode control
inputs to GND (the inputs left unconnected will be inter-
nally pulled up to V
CC
- logic-high). If the M0, M1, and
M2 mode inputs are all unconnected, the MAX13172E
will enter no-cable mode.
Fail-Safe
The MAX13172E guarantees a logic-high receiver out-
put when the receiver inputs are open or shorted, or
when they are connected to a terminated transmission
line with all the drivers disabled. The V.11 receivers
threshold is set between -200mV and -50mV to guaran-
tee fail-safe operation. If the differential receiver input
voltage (B - A) is ≥ -50mV, ROUT is logic-high. In the
case of a terminated bus with all transmitters disabled,
the receiver’s differential input voltage is pulled to 0 by
the termination. With the receiver thresholds of the
MAX13172E, this results in ROUT logic-high.
The V.10 receiver threshold is set between +50mV and
+250mV. If the V.10 receiver input voltage is less than or
equal to +50mV, ROUT is logic-high. The V.28 receiver
threshold is set between 0.8V and 2.0V. If the receiver input
voltage is less than or equal to 0.8V, ROUT is logic-high. In
the case of a terminated bus with transmitters disabled, the
receiver’s input voltage is pulled to 0 by the termination.
ESD Protection
As with all Maxim devices, a minimum of ±2kV-to-GND
ESD-protection structures are incorporated on all pins
to protect against electrostatic discharges encountered
during handling and assembly. The driver outputs and
receiver inputs of the MAX13172E have extra protection
against static electricity. Maxim’s engineers have devel-
oped state-of-the-art structures to protect these pins
against ESD of ±10kV without damage (HBM). The ESD
structures withstand high ESD in all states: normal
operation, shutdown, and powered down. After an ESD
event, the MAX13172E keeps working without latchup
or damage. ESD protection can be tested in various
ways. The transmitter outputs and receiver inputs of the
MAX13172E are characterized for protection to the fol-
lowing limits:
• ±10kV using the Human Body Model
• ±3kV using the Contact Method specified in IEC
61000-4-2
• ±3kV using the Air Gap Discharge Method speci-
fied in IEC 61000-4-2
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents
test setup, test methodology, and test results.
PROTOCOL M2 M1 M0
DCE/
DTE
INVERT T1 T2 T3 R1 R2 R3 T4 R4
Not Used
(Default V.11)
0 0 0 1 0 V.11 V.11 V.11 Z V.11 V.11 V.10 Z
RS-530A 0 0 1 1 0 V.11 V.10 V.11 Z V.10 V.11 V.10 Z
RS-530 0 1 0 1 0 V.11 V.11 V.11 Z V.11 V.11 V.10 Z
X.21 0 1 1 1 0 V.11 V.11 V.11 Z V.11 V.11 V.10 Z
V.35 1 0 0 1 0 V.28 V.28 V.28 Z V.28 V.28 V.28 Z
RS-449/V.36 1 0 1 1 0 V.11 V.11 V.11 Z V.11 V.11 V.10 Z
V.28/RS-232 1 1 0 1 0 V.28 V.28 V.28 Z V.28 V.28 V.28 Z
No Cable 1 1 1 1 0 Z Z Z Z Z Z Z Z
Not Used
(Default V.11)
0 0 0 1 1 V.11 V.11 V.11 Z V.11 V.11 Z V.10
RS-530A 0 0 1 1 1 V.11 V.10 V.11 Z V.10 V.11 Z V.10
RS-530 0 1 0 1 1 V.11 V.11 V.11 Z V.11 V.11 Z V.10
X.21 0 1 1 1 1 V.11 V.11 V.11 Z V.11 V.11 Z V.10
V.35 1 0 0 1 1 V.28 V.28 V.28 Z V.28 V.28 Z V.28
RS-449/V.36 1 0 1 1 1 V.11 V.11 V.11 Z V.11 V.11 Z V.10
V.28/RS-232 1 1 0 1 1 V.28 V.28 V.28 Z V.28 V.28 Z V.28
No Cable 1 1 1 1 1 Z Z Z Z Z Z Z Z
Table 1. Mode Select Table (continued)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

MAX13172ECAI+

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Buy MAX13172ECAI+
Manufacturer:
Maxim Integrated
Description:
Interface - Specialized +5V Multiprotocol, Software-Selectable Clock Transceiver
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