82V3001APVG Datasheet 82V3001APVG, 82V3001APVG8 | P4-P6

List of Figures 4 November 14, 2012

LIST OF FIGURES

Figure - 1 Block Diagram.................................................................................................................................................. 2

Figure - 2 IDT82V3001A SSOP56 Package Pin Assignment........................................................................................... 6

Figure - 3 State Control Block......................................................................................................................................... 10

Figure - 4 State Control Diagram.................................................................................................................................... 11

Figure - 5 TIE Control Circuit Diagram ........................................................................................................................... 12

Figure - 6 State Switch with TIE Control Block Enabled................................................................................................. 13

Figure - 7 State Switch with TIE Control Block Disabled................................................................................................ 13

Figure - 8 DPLL Block Diagram...................................................................................................................................... 14

Figure - 9 Clock Oscillator Circuit................................................................................................................................... 15

Figure - 10 Power-Up Reset Circuit.................................................................................................................................. 15

Figure - 11 IDT82V3001A Power Decoupling Scheme .................................................................................

................... 16

Figure - 12 Input to Output Timing (Normal Mode)........................................................................................................... 25

Figure - 13 Output Timing 1.............................................................................................................................................. 26

Figure - 14 Output Timing 2.............................................................................................................................................. 27

Figure - 15 Input Control Setup and Hold Timing............................................................................................................. 27

List of Tables 5 November 14, 2012

LIST OF TABLES

Table - 1 Pin Description..................................................................................................................................................7

Table - 2 Operating Modes and Status...........................................................................................................................10

Table - 3 Input Reference Frequency Selection.............................................................................................................12

Table - 4 Absolute Maximum Ratings**..........................................................................................................................19

Table - 5 Recommended DC Operating Conditions**....................................................................................................19

Table - 6 DC Electrical Characteristics**........................................................................................................................19

Table - 7 Performance....................................................................................................................................................20

Table - 8 Intrinsic Jitter Unfiltered...................................................................................................................................20

Table - 9 C1.5o (1.544 MHz) Intrinsic Jitter Filtered.......................................................................................................21

Table - 10 C2o (2.048 MHz) Intrinsic Jitter Filtered..........................................................................................................21

Table - 11 8 kHz Input to 8 kHz Output Jitter Transfer.....................................................................................................21

Table - 12 1.544 MHz Input to 1.544 MHz Output Jitter Transfer.....................................................................................21

Table - 13 2.048 MHz Input to 2.048 MHz Output Jitter Transfer.....................................................................................22

Table - 14 8 kHz Input Jitter Tolerance ............................................................................................................................22

Table - 15 1.544 MHz Input Jitter Tolerance....................................................................................................................22

Table - 16 2.048 MHz Input Jitter Tolerance....................................................................................................................23

Table - 17 Timing Parameter Measurement Voltage Levels ............................................................................................24

Table - 18 Input / Output Timing.......................................................................................................................................24

IDT82V3001A PIN CONFIGURATION 6 November 14, 2012

IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT

1 IDT82V3001A PIN CONFIGURATION

Figure - 2 IDT82V3001A SSOP56 Package Pin Assignment

RST

Fref

OSCo

OSCi

F8o

C1.5o

LOCK

C2o

C4o

FLOCK

F_sel1

F_sel0

C3o

C8o

C16o

C32o

F0o

F16o

RSP

TSP

C6o

DDD

TDI

TMS

TRST

TDOTCK

IC0

HOLDOVER

FREERUN

NORMAL

TIE_en

DDD

VSS

MODE_sel0

MODE_sel1

TCLR

DDD

VSS

VDDA

VSS

F32o

VDDA

IC1

IC2

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

82V3001APVG

Mfr. #:

Buy 82V3001APVG

Manufacturer:

IDT

Description:

Clock Generators & Support Products Supports TR62411 WAN PLL Telcordia 2.1Hz

Lifecycle:

New from this manufacturer.

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82V3001APVG

82V3001APVG

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