NVMFD5873NLT1G

NVMFD5873NL
http://onsemi.com
4
TYPICAL CHARACTERISTICS
Q
gs
Figure 7. Capacitance Variation Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V) Q
g
, TOTAL GATE CHARGE (nC)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
R
G
, GATE RESISTANCE (W)
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
1001010.1
0.1
1
10
C, CAPACITANCE (pF)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
t, TIME (ns)
I
S
, SOURCE CURRENT (A)
I
D
, DRAIN CURRENT (A)
V
GS
= 0 V
T
J
= 25°C
C
iss
C
oss
C
rss
V
DS
= 48 V
I
D
= 15 A
V
GS
= 10 V
t
d(on)
t
r
t
f
T
J
= 25°C
V
GS
= 0 V
NVMFD5873NL
FBSOA
T
A
= 25°C, 650 mm
2
,
2 oz Cu Pad, V
GS
= 10 V
0.1 ms
10 ms
1 ms
T
J
= 25°C
V
DS
= 48 V
I
D
= 15 A
0.01 ms
t
d(off)
100
Q
gd
0
500
1000
1500
2000
0 102030405060
0
2
4
6
8
10
0 5 10 15 20 25 30 35
Q
T
1
10
100
1000
1 10 100
0
10
20
30
40
50
60
70
80
0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00
NVMFD5873NL
http://onsemi.com
5
TYPICAL CHARACTERISTICS
Figure 12. Thermal Response
PULSE TIME (sec)
R
(t)
(°C/W)
10%
Duty Cycle = 50%
20%
5%
2%
1%
Single Pulse
0.01
0.1
1
10
100
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
NVMFD5873NL
http://onsemi.com
6
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
CASE 506BT
ISSUE E
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
1.27
0.75
1.40
3.70
4.56
8X
PITCH
6.59
4.84
1.00
DIMENSION: MILLIMETERS
2.30
4X
0.70
5.55
4X
0.56
2X
2.08
2X
M 3.25
h −−−
3.50
−−−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS ARE
A.
1234
56
TOP VIEW
SIDE VIEW
BOTTOM VIEW
D1
E1
h
D
E
B
A
0.20
C
0.20 C
2X
2X
DIM MIN
MILLIMETERS
A 0.90
A1 −−−
b 0.33
c 0.20
D 5.15 BSC
D1 4.70
D2 3.90
E 6.15 BSC
E1 5.70
E2 3.90
e 1.27 BSC
G 0.45
K 0.51
L 0.48
A
0.10 C
0.10 C
14
8
e
8X
D2
b1
E2
b
A0.10 B
C
0.05
C
L
DETAIL A
A1
c
4X
5
MAX
−−−
−−−
0.42
−−−
4.90
4.10
5.90
4.15
0.55
−−−
0.61
M
N 1.80 2.00
78
N
PIN ONE
IDENTIFIER
NOTE 7
NOTE 4
C
SEATING
PLANE
DETAIL A
NOTE 6
4X
K
NOTE 3
D3 1.50 1.70
b1 0.33 0.42
4X
D3
G
4X
DETAIL B
DETAIL B
ALTERNATE
CONSTRUCTION
K1 0.56 −−−
K1
3.75
12
_
MAX
1.10
0.05
0.51
0.33
5.10
4.30
6.10
4.40
0.65
−−−
0.71
2.20
1.90
0.51
−−−
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NVMFD5873NL/D
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NVMFD5873NLT1G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
MOSFET NFET SO8FL 60V 58A 13MOHM
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