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IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
15
Functional Description
The IDT70V3579 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold
times on address, data, and all critical control inputs. All internal
registers are clocked on the rising edge of the clock signal, however,
the self-timed internal write pulse is independent of the LOW to HIGH
transition of the clock signal.
An asynchronous output enable is provided to ease asyn-
chronous bus interfacing. Counter enable inputs are also provided to
stall the operation of the address counters for fast interleaved
memory applications.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce static power consumption.
Multiple chip enables allow easier banking of multiple IDT70V3579s
for depth expansion configurations. Two cycles are required with CE0
LOW and CE1 HIGH to re-activate the outputs.
4830 drw 14
IDT70V3579
CE
0
CE
1
CE
1
CE
0
CE
0
CE
1
A
15
CE
1
CE
0
V
DD
V
DD
IDT70V3579
IDT70V3579
IDT70V3579
Control Inputs
Control Inputs
Control Inputs
Control Inputs
BE,
R/W,
OE,
CLK,
ADS,
CNTRST,
CNTEN
Depth and Width Expansion
The IDT70V3579 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70V3579 can also be used in applications requiring
expanded width, as indicated in Figure 4. Through combining the
control signals, the devices can be grouped as necessary to accom-
modate applications needing 72-bits or wider.
Figure 4. Depth and Width Expansion with IDT70V3579
