6.42
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
10
AC Electrical Characteristics Over the Operating
Temperature Range (Read and Write Cycle Timing)
(1,2)
(VDD = 3.3V ± 150mV, TA = 0°C to +70°C)
NOTES:
1. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE).
2. These values are valid for either level of V
DDQ (3.3V/2.5V). See page 4 for details on selecting the desired I/O voltage levels for each port.
70V3579S4
Com'l Only
70V3579S5
Com'l
& Ind
70V3579S6
Com'l Only
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
t
CYC2
Clock Cycle Time (Pipelined) 7.5
____
10
____
12
____
ns
t
CH2
Clock High Time (Pipelined) 3
____
4
____
5
____
ns
t
CL 2
Clock Low Time (Pipelined) 3
____
4
____
5
____
ns
t
R
Clock Rise Time
____
3
____
3
____
3ns
t
F
Clock Fall Time
____
3
____
3
____
3ns
t
SA
Address Setup Time 1.8
____
2.0
____
2.0
____
ns
t
HA
Address Hold Time 0.7
____
0.7
____
1.0
____
ns
t
SC
Chip Enable Setup Time 1.8
____
2.0
____
2.0
____
ns
t
HC
Chip Enable Hold Time 0.7
____
0.7
____
1.0
____
ns
t
SB
Byte Enable Setup Time 1.8
____
2.0
____
2.0
____
ns
t
HB
Byte Enable Hold Time 0.7
____
0.7
____
1.0
____
ns
t
SW
R/W Setup Time 1.8
____
2.0
____
2.0
____
ns
t
HW
R/W Hold Time 0.7
____
0.7
____
1.0
____
ns
t
SD
Input Data Setup Time 1.8
____
2.0
____
2.0
____
ns
t
HD
Input Data Hold Time 0.7
____
0.7
____
1.0
____
ns
t
SAD
ADS Setup Time
1.8
____
2.0
____
2.0
____
ns
t
HA D
ADS Hold Time
0.7
____
0.7
____
1.0
____
ns
t
SCN
CNTEN Setup Time
1.8
____
2.0
____
2.0
____
ns
t
HC N
CNTEN Hold Time
0.7
____
0.7
____
1.0
____
ns
t
SRST
CNTRST Setup Time
1.8
____
2.0
____
2.0
____
ns
t
HRST
CNTRST Hold Time
0.7
____
0.7
____
1.0
____
ns
t
OE
(1)
Output Enable to Data Valid
____
4
____
5
____
6ns
t
OLZ
Output Enable to Output Low-Z 0
____
0
____
0
____
ns
t
OHZ
Output Enable to Output High-Z 1 4 1 4.5 1 5 ns
t
CD2
Clock to Data Valid (Pipelined)
____
4.2
____
5
____
6ns
t
DC
Data Output Hold After Clock High 1
____
1
____
1
____
ns
t
CKHZ
Clock High to Output High-Z 1 3 1 4.5 1.5 6 ns
t
CKLZ
Clock High to Output Low-Z 1
____
1
____
1
____
ns
Port-to-Port Delay
t
CO
Clock-to-Clock Offset 6
____
8
____
10
____
ns
4830 tbl 11