LTC4318
7
4318fa
For more information www.linear.com/LTC4318
The LTC4318 is an I
2
C/SMBus address translator. It bridges
two segments of an I
2
C bus, reading incoming addresses
on the master side and retransmitting them to the slave
side with the 7-bit I
2
C addresses translated in real time.
This allows multiple I
2
C devices with the same address
to be connected to the same bus without interference.
The translated addresses are configured with external
resistors, and no extra software is required. An ENABLE
pin allows bus segments to be enabled and disabled, and
the LTC4318 allows hot swapping isolated bus segments
together.
Figure 1 shows an I
2
C master connected to the input bus
of the LTC4318 (SCLIN and SDAIN). The slave devices
requiring address translation are connected to the output
bus of the LTC4318 (SCLOUT and SDAOUT). Any other
slave devices that do not require address translation are
placed together with the master on the input bus of the
LTC4318. Two switches (N1 and N2) inside the LTC4318
connect the input bus to the output bus. N1 connects
operaTion
SCLIN to SCLOUT while N2 connects SDAIN to SDAOUT.
In most conditions, N1 and N2 stay on so that the input
and output buses are connected.
Translation starts when the master issues a START bit
(SDAIN goes low while SCLIN is high). The LTC4318
turns off N2 to disconnect SDAIN from SDAOUT. As the
master sends the address byte, the LTC4318 translates
the incoming address at the SDAIN pin to a new address
at the SDAOUT pin by XORing each incoming bit with
a user-configurable translation byte, one bit at a time.
N3 turns on and off to send out the new address to the
SDAOUT pin. Once all 7 bits of the address are processed,
the LTC4318 turns on N2 again to reconnect SDAIN to
SDAOUT. The master then transmits the R/W bit directly
to the slave. If the new, translated address on SDAOUT
matches the slaves address, the slave pulls SDAOUT low
to acknowledge (ACK bit). N2 remains on and the rest of
the data bytes are transmitted unmodified between the
master and slave. The address translation process restarts
when the master issues a new START bit.
Figure 1. Basic Functions of the LTC4318
4318 F01
V
CC1
MASTER
SCLOUT
SDAOUT
SCLIN
SDAIN
V
CC2
SLAVE
#1
LTC4318
SLAVE
#2
7-BIT ADDRESS
TRANSLATION
BYTE SHIFT REGISTER
0000010
ENABLE
ADDRESS
TRANSLATION
N3
1.8V
CMP2
+
XOR
N1
N2
LTC4318
8
4318fa
For more information www.linear.com/LTC4318
operaTion
Figure 2 shows typical waveforms for the circuit on the
front page. In this example, the master transmits address
0x34 while the slave is configured to respond to address
0x36. The resistive dividers at the XORL and XORH pins are
configured to generate an address translation byte of 0x02.
Note that in this example, the 8-bit hexadecimal address
format (with R/W = 0) is used. 7-bit addresses are also
commonly found in I
2
C device documentation. Make sure
to use the correct format when calculating the address
translation byte. Table 1 shows examples of both formats.
Figure 2. Basic Address Translation Waveforms
TRANSLATION
BYTE
SDAOUT
SCLIN
SDAIN
ADDRESS BITSSTART
a6 a5 a4 a3 a2 a1 a0
0 1 1 0 1 0 0
0 0 0 0 0 1 0
0
0
0
0 1 1 0 1 1 0
= 0x34
= 0x02
= 0x36
4318 F02
N2 GATE N2 ON N2 ON N2 OFF
R/W
BIT
ACK
BIT
Table 1.
DESCRIPTION
BINARY ADDRESS 7-BIT HEX ADDRESS
WITHOUT R/W
8-BIT HEX ADDRESS
WITH R/W = 0
a6 a5 a4 a3 a2 a1 a0 R/W
Input Address from SDAIN 0 0 1 1 0 1 0 0 0x1A 0x34
Translation Byte 0 0 0 0 0 0 1 0 0x01 0x02
Output Address to SDAOUT 0 0 1 1 0 1 1 0 0x1B 0x36
LTC4318
9
4318fa
For more information www.linear.com/LTC4318
Figure 4. Two Slaves Sharing One Channel of LTC4318
Figure 3. Two Independent Address Translation
operaTion
SCL
SDA
4318 F03
MASTER
SCLOUT1
SDAOUT1
SCLIN1
SDAIN1
SCL
SDA
SLAVE
#1
LTC4318
SCLIN2
SDAIN2
SCLOUT2
SDAOUT2
SLAVE #3
INPUT ADDRESS
0x36
TRANSLATION BYTE
0x02
SCL
SDA
SLAVE
#3
SCL
SDA
SLAVE
#2
HARDWIRED ADDRESS
0x34
SLAVE #1
INPUT ADDRESS
0x32
TRANSLATION BYTE
0x06
HARDWIRED ADDRESS
0x34
HARDWIRED ADDRESS
0x34
00110010
00000110
00110100
00110110
00000010
00110100
SCL
SDA
4318 F04
MASTER
SCL
SDA
SLAVE
#2
SCLOUT
SDAOUT
SCLIN
SDAIN
SCL
SDA
SLAVE
#1
LTC4318
SCL
SDA
SLAVE
#3
HARDWIRED ADDRESS
0x34
TRANSLATION BYTE
0x02
SLAVE #1
INPUT ADDRESS
0x36
SLAVE #3
INPUT ADDRESS
0x32
HARDWIRED ADDRESS
0x34
HARDWIRED ADDRESS
0x30
00110110
00000010
00110100
00110010
00000010
00110000
System Configurations
There are several ways that individual slaves or banks of
slaves can be connected to an LTC4318. In Figure 3, each
slave is paired with one channel of the LTC4318. This
configuration allows for maximum flexibility in allocating
the bus addresses. Both read and write operations and all
protocols supported by the LTC4318 are allowed. Figure4
shows two slaves with different hardwired addresses
translated to two different addresses using one channel of
the LTC4318 and a common translation byte. A program
is available to help the user visualize an I
2
C bus with the
LTC4318; this program can be found in the following link:
www.linear.com/TranslatorTool
Setting the Translation Byte
When the LTC4318 is first powered up or any time a rising
edge is detected on the ENABLE pin, the LTC4318 reads
the voltages at the XORH and XORL pins to determine the
7-bit translation byte. These voltages are referenced to
V
CC
so a resistive divider at each of these pins is the most
convenient way to set the voltages. The required transla-
tion byte can be determined by taking the bitwise XOR of
the slave
s original address and the desired input address.
The voltages at the XORH and XORL pins configure the
translation byte. The XORL voltage configures the lower4
translation bits (excluding the R/W bit), while the XORH
voltage configures the upper 3 translation bits. T
ables 2
and 3 show the recommended resistive divider values. R
LT
and R
LB
are the top and bottom resistors connected to
XORL, while R
HT
and R
HB
are the top and bottom resistors
connected to XORH (Figure 5). Use 1% tolerance resistors
for R
LT
, R
LB
, R
HT
and R
HB
.
Figure 5. Address Translation Byte Configuration Resistors
4318 F05
V
CC
R
HT
R
LT
XORLXORH
LTC4318
V
CC
R
HB
R
LB

LTC4318CUF#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Interface - Specialized 2x I2C/SMBus Address Translator
Lifecycle:
New from this manufacturer.
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