FEMTOCLOCK
®
CRYSTALl-TO-3.3V LVPECL CLOCK GENERATOR 10 REVISION B 10/29/15
843251I-04 DATA SHEET
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination
R1
84
R2
84
3.3V
R3
125
R4
125
Z
o
= 50
Z
o
= 50
Input
3.3V
3.3V
+
_
REVISION B 10/29/15 11 FEMTOCLOCK
®
CRYSTALL-TO-3.3V LVPECL CLOCK GENERATOR
843251I-04 DATA SHEET
Schematic Example
Figure 5 shows an example of 843251I-04 application schematic.
In this example, the device is operated at V
CC
= 3.3V. The 18pF
parallel resonant 25MHz crystal is used. The C1 = 33pF and C2 =
27pF are recommended for frequency accuracy. For different
board layout, the C1 and C2 may be slightly adjusted for optimizing
frequency accuracy. Two examples of LVPECL termination are
shown in this schematic. Additional termination approaches are
shown in the LVPECL Termination Application Note.
Note: Thermal pad (E-pad) must be connected to ground (V
EE
).
Figure 5. 843251I-04 Schematic Example
3.3V
VCC
R7
50
R8
50
Zo = 50 Ohm
Zo = 50 Ohm
+
-
R6
50
VCC
To Logic
Input
pins
To Logic
Input
pins
Logi c Control Inpu t Ex am ples
Set Logic
Inp ut t o
'0 '
Set Logic
Input to
'1'
R3
13 3
R5
82 .5
+
-
RU 2
Not Ins tall
RU 1
1k
C1
33pF
R2
133
RD 2
1k
RD 1
Not Inst all
X1
25 MH z
Zo = 50 Ohm
Zo = 50 Ohm
C2
27 pF
R4
82.5
VCC VCC
FREQ_SEL
VCC
C3
0.1uF
VCC
U1
ICS8 43 25 1I -0 4
VCC A
1
VEE
2
XT A L_ OU T
3
XT A L_ I N
4
VCC
8
Q
7
nQ
6
FREQ_SEL
5
Optional
Y-Termination
VCC=3.3V
C5
10u
R1
10
C4
0. 1u
VCC A
843251I-04
FEMTOCLOCK
®
CRYSTALl-TO-3.3V LVPECL CLOCK GENERATOR 12 REVISION B 10/29/15
843251I-04 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 843251I-04.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 843251I-04 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 70mA = 242.55mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
Total Power_
MAX
(3.3V, with all outputs switching) = 242.55mW + 30mW = 272.55mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the
bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 129.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.273W * 129.5°C/W = 120.4°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (multi-layer).
Table 6. Thermal Resistance
JA
for 8 Lead TSSOP, Forced Convection
JA
vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 129.5°C/W 125.5°C/W 123.5°C/W

843251AGI-04LFT

Mfr. #:
Manufacturer:
Description:
Clock Generators & Support Products 1 LVPECL OUT SYNTHESIZER
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