PRODUCT SPECIFICATION FAN4810
REV. 1.0.12 9/24/03 7
Power Factor Correction
Power factor correction makes a nonlinear load look like a
resistive load to the AC line. For a resistor, the current drawn
from the line is in phase with and proportional to the line
voltage, so the power factor is unity (one). A common class
of nonlinear load is the input of most power supplies, which
use a bridge rectifier and capacitive input filter fed from the
line. The peak-charging effect, which occurs on the input
filter capacitor in these supplies, causes brief high-amplitude
pulses of current to flow from the power line, rather than
a sinusoidal current inphase with the line voltage. Such
supplies present a power factor to the line of less than one
(i.e. they cause significant current harmonics of the power
line frequency to appear at their input). If the input current
drawn by such a supply (or any other nonlinear load) can be
made to follow the input voltage in instantaneous amplitude,
it will appear resistive to the AC line and a unity power factor
will be achieved.
To hold the input current draw of a device drawing power
from the AC line in phase with and proportional to the input
voltage, a way must be found to prevent that device from
loading the line except in proportion to the instantaneous
line voltage. The PFC of the FAN4810 uses a boost-mode
DC-DC converter to accomplish this. The input to the
converter is the full wave rectified AC line voltage. No bulk
filtering is applied following the bridge rectifier, so the input
voltage to the boost converter ranges (at twice line
frequency) from zero volts to the peak value of the AC input
and back to zero. By forcing the boost converter to meet two
simultaneous conditions, it is possible to ensure that the
current drawn from the power line is proportional to the
input line voltage. One of these conditions is that the output
voltage of the boost converter must be set higher than the
peak value of the line voltage. A commonly used value is
385VDC, to allow for a high line of 270VAC
rms
. The other
condition is that the current drawn from the line at any given
instant must be proportional to the line voltage. Establishing
a suitable voltage control loop for the converter, which in
turn drives a current error amplifier and switching output
driver satisfies the first of these requirements. The second
requirement is met by using the rectified AC line voltage to
modulate the output of the voltage control loop. Such
modulation causes the current error amplifier to command a
power stage current that varies directly with the input
voltage. In order to prevent ripple, which will necessarily
appear at the output of the boost circuit (typically about
10VAC on a 385V DC level), from introducing distortion
back through the voltage error amplifier, the bandwidth of
the voltage loop is deliberately kept low. A final refinement
is to adjust the overall gain of the PFC such to be propor-
tional to 1/V
IN
2, which linearizes the transfer function of the
system as the AC input voltage varies.
Since the boost converter topology in the FAN4810 PFC is
of the current-averaging type, no slope compensation is
required.
PFC Circuit Blocks
Gain Modulator
Figure 1 shows a block diagram of the FAN4810. The gain
modulator is the heart of the PFC, as it is this circuit block
which controls the response of the current loop to line
voltage waveform and frequency, rms line voltage, and PFC
output voltage. There are three inputs to the gain modulator.
These are:
1. A current representing the instantaneous input voltage
(amplitude and waveshape) to the PFC. The rectified AC
input sine wave is converted to a proportional current
via a resistor and is then fed into the gain modulator at
I
AC
. Sampling current in this way minimizes ground
noise, as is required in high power switching power con-
version environments. The gain modulator responds lin-
early to this current.
2. A voltage proportional to the long-term RMS AC line
voltage, derived from the rectified line voltage after
scaling and filtering. This signal is presented to the gain
modulator at V
RMS
. The gain modulator’s output is
inversely proportional to V
RMS
2
(except at unusually
low values of V
RMS
where special gain contouring
takes over, to limit power dissipation of the circuit
components under heavy brownout conditions). The
relationship between V
RMS
and gain is called K, and is
illustrated in the Typical Performance Characteristics.
3. The output of the voltage error amplifier, VEAO. The
gain modulator responds linearly to variations in this
voltage.
The output of the gain modulator is a current signal, in the
form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual-ground
(negative) input of the current error amplifier. In this way
the gain modulator forms the reference for the current error
loop, and ultimately controls the instantaneous current draw
of the PFC from the power line. The general form for the
output of the gain modulator is:
More exactly, the output current of the gain modulator is
given by:
where K is in units of V
-1
.
Note that the output current of the gain modulator is limited
to 500µA.
I
GAINMOD
I
AC
VEAO×
V
RMS
2
1V×=
(1)
I
GAINMOD
K VEAO 0.625V()× I
AC
×=
FAN4810 PRODUCT SPECIFICATION
8 REV. 1.0.12 9/24/03
Current Error Amplifier
The current error amplifier’s output controls the PFC duty
cycle to keep the average current through the boost inductor
a linear function of the line voltage. At the inverting input to
the current error amplifier, the output current of the gain
modulator is summed with a current which results from a
negative voltage being impressed upon the I
SENSE
pin. The
negative voltage on I
SENSE
represents the sum of all currents
flowing in the PFC circuit, and is typically derived from a
current sense resistor in series with the negative terminal of
the input bridge rectifier. In higher power applications, two
current transformers are sometimes used, one to monitor the
ID of the boost MOSFET(s) and one to monitor the I
F
of the
boost diode. As stated above, the inverting input of the
current error amplifier is a virtual ground. Given this fact,
and the arrangement of the duty cycle modulator polarities
internal to the PFC, an increase in positive current from the
gain modulator will cause the output stage to increase its
duty cycle until the voltage on I
SENSE
is adequately negative
to cancel this increased current. Similarly, if the gain
modulator’s output decreases, the output duty cycle will
decrease, to achieve a less negative voltage on the I
SENSE
pin.
Cycle-By-Cycle Current Limiter
The I
SENSE
pin, as well as being a part of the current feed-
back loop, is a direct input to the cycle-by-cycle current
limiter for the PFC section. Should the input voltage at this
pin ever be more negative than -1V, the output of the PFC
will be disabled until the protection flip-flop is reset by the
clock pulse at the start of the next PFC power cycle.
TriFault Detect
TM
To improve power supply reliability, reduce system
component count, and simplify compliance to UL 1950
safety standards, the FAN4810 includes TriFault Detect.
This feature monitors VFB (Pin 15) for certain PFC fault
conditions.
In the case of a feedback path failure, the output of the PFC
could go out of safe operating limits. With such a failure,
VFB will go outside of its normal operating area. Should
VFB go too low, too high, or open, TriFault Detect senses the
error and terminates the PFC output drive.
TriFault detect is an entirely internal circuit. It requires no
external components to serve its protective function.
Overvoltage Protection
The OVP comparator serves to protect the power circuit
from being subjected to excessive voltages if the load should
suddenly change. A resistor divider from the high voltage
DC output of the PFC is fed to V
FB
. When the voltage on
V
FB
exceeds 2.75V, the PFC output driver is shut down.
The OVP comparator has 250mV of hysteresis, and the PFC
will not restart until the voltage at V
FB
drops below 2.50V.
The V
FB
should be set at a level where the active and passive
external power components and the FAN4810 are within
their safe operating voltages, but not so low as to interfere
with the boost voltage regulation loop.
Figure 1. PFC Block Diagram
15
VEAO
IEAO
V
FB
I
AC
V
RMS
I
SENSE
RAMP 1
OSCILLATOR
OVP
PFC I
LIMIT
TRI-FAULT
2.5V
+
+
16
2
4
3
VEA
7
+
IEA
1
+
+
PFC OUT
12
S
R
Q
Q
S
R
Q
Q
2.75V
1V
+
0.5V
1.6k
1.6k
GAIN
MODULATOR
PRODUCT SPECIFICATION FAN4810
REV. 1.0.12 9/24/03 9
Error Amplifier Compensation
The output of the PFC is typically loaded by a PWM
converter to produce the low voltages and high currents
required at the outputs of a SMPS. PWM loading of the
PFC can be modeled as a negative resistor; an increase in
input voltage to the PWM causes a decrease in the input
current. This response dictates the proper compensation of
the two transconductance error amplifiers. Figure 2 shows
the types of compensation networks most commonly used
for the voltage and current error amplifiers, along with their
respective return points. The current loop compensation is
returned to V
REF
to produce a soft-start characteristic on the
PFC: as the reference voltage comes up from zero volts, it
creates a differentiated voltage on IEAO which prevents the
PFC from immediately demanding a full duty cycle on its
boost converter. There are two major concerns when
compensating the voltage loop error amplifier; stability and
transient response. Optimizing interaction between transient
response and stability requires that the error amplifier’s
open-loop crossover frequency should be 1/2 that of the line
frequency, or 23Hz for a 47Hz line (lowest anticipated
international power frequency). The gain vs. input voltage
of the FAN4810’s voltage error amplifier has a specially
shaped non-linearity such that under steady-state operating
conditions the transconductance of the error amplifier is at a
local minimum. Rapid perturbations in line or load condi-
tions will cause the input to the voltage error amplifier (V
FB
)
to deviate from its 2.5V (nominal) value. If this happens,
thetransconductance of the voltage error amplifier will
increase significantly, as shown in the Typical Performance
Characteristics. This raises the gain-bandwidth product of
the voltage loop, resulting in a much more rapid voltage loop
response to such perturbations than would occur with a
conventional linear gain characteristic.
The current amplifier compensation is similar to that of the
voltage error amplifier with the exception of the choice of
crossover frequency. The crossover frequency of the current
amplifier should be at least 10 times that of the voltage
amplifier,to prevent interaction with the voltage loop.
It should also be limited to less than 1/6th that of the
switching frequency, e.g. 16.7kHz for a 100kHz switching
frequency.
There is a modest degree of gain contouring applied to the
transfer characteristic of the current error amplifier, to
increase its speed of response to current-loop perturbations.
However, the boost inductor will usually be the dominant
factor in overall current loop response. Therefore, this
contouring is significantly less marked than that of the
voltage error amplifier. This is illustrated in the Typical
Performance Characteristics.
For more information on compensating the current and
voltage control loops, see Application Note AN42045.
Application Note 42030 also contains valuable information
for the design of this class of PFC.
Figure 2. Compensation Network Connections for the
Voltage and Current Error Amplifiers
Figure 3. External Component Connections to V
CC
15
VEAO
IEAO
V
FB
I
AC
V
RMS
I
SENSE
2.5V
+
16
2
4
3
VEA
+
IEA
+
V
REF
1
PFC
OUTPUT
GAIN
MODULATOR
FAN4810
V
CC
GND
V
BIAS
0.22µF
CERAMIC
15V
ZENER
R
BIAS

FAN4810MX

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Power Factor Correction - PFC PFC Preregulator
Lifecycle:
New from this manufacturer.
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