LTC1272
19
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APPLICATIONS INFORMATION
If the clock signal for the AD7572 is derived from a separate
crystal or other signal which is not synchronous with the
microprocessor clock, then the signals need to be synchro-
nized for the LTC1272 to achieve best analog performance
(see Clock and Control Synchronization). The best way
to synchronize these signals is to drive the CLK IN pin of
the LTC1272 with a derivative of the processor clock, as
mentioned above and shown in Figure 22. Another way,
shown in Figure 23, is to use a flip-flop to synchronize the
RD to the LTC1272 with the CLK IN signal. This method
will work but has two disavantages over the first: because
the RD is delayed by the flip-flop, the actual conversion
start and the enabling of the LTC1272’s BUSY and data
outputs can take up to one CLK IN cycle to respond to a
RD convert command from the processor. The sampling
of the analog input no longer occurs at the processors
falling RD edge but may be delayed as much as one CLK
IN cycle. Although the LTC1272 will still exhibit excellent
DC performance, the flip-flop will introduce jitter into the
sampling which may reduce the usefulness of this method
for AC systems.
Figure 22. Plugging the LTC1272 into an AD7572 Socket
Case 1: Clock Synchronous with CS and RD
10µF
IN
REF
D11 (MSB)
D10
D9
D8
D7
CLK IN**
CLK OUT
HBEN
RD
CS
BUSY
NC
V
LTC1272
D6
D5
D4
DGND
D3/11
D2/10
D1/9
D0/8
A
V
AGND
DD
µP
CONTROL
LINES
0.1µF
–15V
µP
DATA
BUS
ANALOG INPUT
(0V TO 5V)
10µF
0.1µF
THE LTC1272 HAS THE SAME 0V TO 5V INPUT RANGE BUT PROVIDES A 2.42V
REFERENCE OUTPUT AS OPPOSED TO THE –5.25V OF THE AD7572. FOR PROPER
OPERATION, REVERSE THE REFERENCE CAPACITOR POLARITY AND SHORT OUT THE
10Ω RESISTOR.
*
THE ADC CLOCK SHOULD BE SYNCHRONIZED TO THE CONVERSION START
SIGNALS (CS, RD) OR 1-2 LSBs OF OUTPUT CODE NOISE MAY OCCUR. DERIVING
THE ADC CLOCK FROM THE µP CLOCK IS ADEQUATE.
**
THE LTC1272 CAN ACCOMMODATE THE –15V SUPPLY OF THE AD7572 BUT DOES
NOT REQUIRE IT. PIN 23 OF THE LTC1272 IS NOT INTERNALLY CONNECTED.
LTC1272 • F22
2.42V
V
OUTPUT
*
REF
10Ω*
+
10µF
0.1µF
5V
+
+
LTC1272
20
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APPLICATIONS INFORMATION
Figure 23. Plugging the LTC1272 into an AD7572 Socket
Case 2: Clock Not Synchronous with CS and RD
EXTERNAL
ASYNCHRONOUS
CLOCK
10µF
IN
REF
D11 (MSB)
D10
D9
D8
D7
CLK IN
CLK OUT
HBEN
RD
CS
BUSY
NC
V
LTC1272
D6
D5
D4
DGND
D3/11
D2/10
D1/9
D0/8
A
V
AGND
DD
µP
CONTROL
LINES
0.1µF
–15V
µP
DATA
BUS
ANALOG INPUT
(0V TO 5V)
10µF
THE LTC1272 HAS THE SAME 0V TO 5V INPUT RANGE BUT PROVIDES A 2.42V
REFERENCE OUTPUT AS OPPOSED TO THE –5.25V OF THE AD7572. FOR PROPER
OPERATION, REVERSE THE REFERENCE CAPACITOR POLARITY AND SHORT OUT THE
10Ω RESISTOR.
*
THE D FLIP-FLOP SYNCHRONIZES THE CONVERSION START SIGNAL (RD ) TO THE
ADC CLK SIGNAL TO PREVENT OUTPUT CODE NOISE WHICH OCCURS WITH
AN ASYNCHRONOUS CLOCK.
**
THE LTC1272 CAN ACCOMMODATE THE –15V SUPPLY OF THE AD7572 BUT DOES
NOT REQUIRE IT. PIN 23 OF THE LTC1272 IS NOT INTERNALLY CONNECTED.
LTC1272 • F23
2.42V
V
OUTPUT
*
REF
10Ω*
0.1µF
+
10µF
0.1µF
5V
+
OUT
74HC04
RD
S
Q
D**
CLK
1/2
74HC74
OR
+
LTC1272
21
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
C 01/13 Edited text in the Dynamic Accuracy table heading to remove reference to the 166kHz (LTC1272-5) version. 3
(Revision history begins at Rev C)

LTC1272-3ACSW#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-bit 250ksps SAR ADC (3us Conversion Time)
Lifecycle:
New from this manufacturer.
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