OMO ElectronicOMO Electronic
Expand menu
0 Cart

TDA7575

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
TDA7575
4/17
V
MC
Maximum common mode input
level
f = 1kHz 1 Vrms
SR Slew Rate 1.5 4 V/µs
∆V
PM
Mute/Unmute Transient A-weighted -100 0 100 mVpp
∆V
TO
Mute/Stand-by Transient A-weighted -100 0 100 mVpp
T
ON
Turn on Delay D2 (IB1) 0 to 1 15 40 ms
T
OFF
Turn off Delay D2 (IB1) 1 to 0 15 40 ms
V
OFF
St-By pin for St-By 0 1.5 V
V
SB
St-By pin for standard bridge 3.5 5 V
V
HE
St-By pin for Hi-eff 7 18 V
I
O
St-By pin Current 1.5 < V
stby/HE
< 18V 7 160 200 µA
St-By Pin Current V
stby
< 1.5V -10 0 10 µA
V
m
Mute pin voltage for mute mode 0 1.5 V
V
m
Mute pin voltage for play mode 3.5 18 V
I
m
Mute pin current (ST_BY) V
mute
= 0V, V
stby
< 1.5V -5 0 5 µA
I
m
Mute pin current (operative) 0V < V
mute
< 18V, V
stby
> 3.5V 65 100 µA
V
I2C
I2C pin voltage for I2C disabled 0 1.5 V
V
I2C
I2C pin voltage for I2C enabled 2.5 18 V
I2C I2C pin current (stby) 0V < I2C EN < 18V, V
stby
< 1.5V -5 0 5 µA
I2C I2C pin current (operative) I2C EN <18V, V
stby
>3.5V 7 11 15 µA
V
1OHM
1OHM pin voltage for 2ch mode 0 1.5 V
V
1OHM
1OHM pin voltage for 1ohm
mode
2.5 18 V
I
1OHM
1OHM pin current (stby) 0V < 1OHM <18V, V
stby
< 1.5V -5 0 5 µA
I
1OHM
1OHM pin current (operative) 1OHM <18V, V
stby
> 3.5V 7 11 15 µA
La A Pin Voltage Low logic level 0 1.5 V
Ha High logic level 2.5 18 V
Ia A Pin Current (ST-BY) 0V < A < 18V, V
stby
< 1.5V -5 0 5 µA
Ia A Pin Current (Operative) A<18V, V
stby
> 3.5V 7 11 15 µA
Lb B Pin Voltage Low logic level 0 1.5 V
Hb High logic level 2.5 18 V
Ib B Pin Current (ST-BY) 0V < B < 18V, V
stby
< 1.5V -5 0 5 µA
Ib B Pin Current (Operative) B < 18V, V
stby
> 3.5V 7 11 15 µA
T
W
Thermal warning 150 °C
T
PI
Thermal Protection intervention 170 °C
I
CDH
Clip Pin High Leakage Current CD off, 0V < V
CD
< 5.5V -15 0 15 µA
Symbol Parameter Test Condition Min. Typ. Max. Unit
ELECTRICAL CHARACTERISTCS:
(continued)
5/17
TDA7575
I
CDL
Clip Pin Low Sink Current CD on; V
CD
< 300mV 1 mA
CD Clip detect THD level D0 (IB1) = 0 0.8 1.3 2.5 %
D0 (IB1) = 1 5 10 15 %
(*) ST-BY Pin high enables I2C bus; ST-BY Pin low puts the device in ST-BY condition.(see “prog” for more details)
TURN ON DIAGNOSTICS (Power Amplifier Mode)
Pgnd Short to GND det. (below this
limit, the Output is considered in
Short Circuit to GND)
Power Amplifier in st-by condition 1.2 V
Pvs Short to Vs det. (above this
limit, the Output is considered in
Short Circuit to VS)
V
s
-0.9 V
Pnop Normal operation
thresholds.(Within these limits,
the Output is considered
without faults).
1.8 V
s
-1.5 V
Lsc Shorted Load det. 0.5 Ω
Lop Open Load det. 130 Ω
Lnop Normal Load det. 1.5 70 Ω
TURN ON DIAGNOSTICS (Line Driver Mode)
Pgnd Short to GND det. (below this
limit, the Output is considered in
Short Circuit to GND)
Power Amplifier in st-by 1.2 V
Pvs Short to Vs det. (above this
limit, the Output is considered in
Short Circuit to VS)
V
s
-0.9 V
Pnop Normal operation
thresholds.(Within these limits,
the Output is considered
without faults).
1.8 V
s
-1.5 V
Lsc Shorted Load det. 1.5 Ω
Lop Open Load det. 400 Ω
Lnop Normal Load det. 4.5 200 Ω
PERMANENT DIAGNOSTICS (Power Amplifier Mode or Line Driver Mode)
Pgnd Short to GND det. (below this
limit, the Output is considered in
Short Circuit to GND)
Power Amplifier in Mute or Play
condition, one or more short circuits
protection activated
1.2 V
Pvs Short to Vs det. (above this
limit, the Output is considered in
Short Circuit to VS)
V
s
- 0.9
V
Pnop Normal operation
thresholds.(Within these limits,
the Output is considered
without faults).
1.8 V
s
-1.5 V
Lsc Shorted Load det. Pow. Amp. mode 0.5 Ω
Line Driver mode 1.5 Ω
Symbol Parameter Test Condition Min. Typ. Max. Unit
ELECTRICAL CHARACTERISTCS:
(continued)
TDA7575
6/17
I
2
C BUS INTERFACE
Data transmission from microprocessor to the TDA7575 and viceversa takes place through the 2 wires I
2
C BUS inter-
face, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected).
Data Validity
As shown by fig. 1, the data on the SDA line must be stable during the high period of the clock.
The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
Start and Stop Conditions
As shown by fig. 2 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH.
The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transferred first.
Acknowledge
The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig.3). The
receiver** the acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that
the SDAline is stable LOW during this clock pulse.
* Transmitter
=master (
µ
P) when it writes an address to the TDA7575
= slave (TDA7575) when the
µ
P reads a data byte from TDA7575
** Receiver
= slave (TDA7575) when the
µ
P writes an address to the TDA7575
= master (mP) when it reads a data byte from TDA7575
V
O
Offset Detection Power Amplifier in play condition
AC Input signals = 0
±1.5 ±2 ±2.5 V
I
2
C BUS INTERFACE
f
SCL
Clock Frequency 400 KHz
V
IL
Input Low Voltage 1.5 V
V
IH
Input High Voltage 2.3 V
Symbol Parameter Test Condition Min. Typ. Max. Unit
ELECTRICAL CHARACTERISTCS:
(continued)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

TDA7575

Mfr. #:
Buy TDA7575
Manufacturer:
STMicroelectronics
Description:
IC AMP AUDIO 150W AB 27FLEXIWATT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet