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X5163S8Z-2.7A

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
13
FN8128.4
August 13, 2015
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5V
OUTPUT
100pF
5V
3.3k
RESET/RESET
30pF
1.64k
1.64k
FIGURE 10. EQUIVALENT A.C. LOAD CIRCUIT AT 5V V
CC
A.C. Test Conditions
Input pulse levels V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times 10ns
Input and output timing level V
CC
x0.5
AC Electrical Specifications Serial Input Timing (Over operating conditions unless otherwise specified.)
SYMBOL PARAMETER
2.7-5.5V
UNITMIN MAX
f
SCK
Clock Frequency 0 2 MHz
t
CYC
Cycle Time 500 ns
t
LEAD
CS Lead Time 250 ns
t
LAG
CS Lag Time 250 ns
t
WH
Clock HIGH Time 200 ns
t
WL
Clock LOW Time 200 ns
t
SU
Data Setup Time 50 ns
t
H
Data Hold Time 50 ns
t
RI
(3)
Input Rise Time 100 ns
t
FI
(3)
Input Fall Time 100 ns
t
CS
CS Deselect Time 500 ns
t
WC
(4)
Write Cycle Time 10 ms
SCK
CS
SI
SO
MSB IN
t
SU
t
RI
t
LAG
t
LEAD
t
H
LSB IN
t
CS
t
FI
HIGH IMPEDANCE
FIGURE 11. SERIAL INPUT TIMING
X5163, X5165
14
FN8128.4
August 13, 2015
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AC Electrical Specifications Serial Output Timing(Over operating conditions unless otherwise specified.)
SYMBOL PARAMETER
2.7-5.5V
UNITMIN MAX
f
SCK
Clock Frequency 0 2 MHz
t
DIS
Output Disable Time 250 ns
t
V
Output Valid from Clock Low 200 ns
t
HO
Output Hold Time 0 ns
t
RO
(3)
Output Rise Time 100 ns
t
FO
(3)
Output Fall Time 100 ns
NOTES:
3. This parameter is periodically sampled and not 100% tested.
4. t
WC
is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
SCK
CS
SO
SI
MSB OUT MSB–1 OUT LSB OUT
ADDR
LSB IN
t
CYC
t
V
t
HO
t
WL
t
WH
t
DIS
t
LAG
TABLE 3. SERIAL OUTPUT TIMING
V
CC
t
PURST
t
PURST
t
R
t
F
t
RPD
RESET (X5163)
0 Volts
V
TRIP
V
TRIP
RESET (X5165)
TABLE 4. POWER-UP AND POWER-DOWN TIMING
X5163, X5165
15
FN8128.4
August 13, 2015
Submit Document Feedback
RESET Output Timing
SYMBOL PARAMETER MIN TYP MAX UNIT
V
TRIP
Reset Trip Point Voltage, X5163-4.5A, X5163-4.5A
Reset Trip Point Voltage, X5163, X5165
Reset Trip Point Voltage, X5163-2.7A, X5165-2.7A
Reset Trip Point Voltage, X5163-2.7, X5165-2.7
4.5
4.25
2.85
2.55
4.63
4.38
2.92
2.63
4.75
4.5
3.0
2.7
V
V
TH
V
TRIP
Hysteresis (HIGH to LOW vs. LOW to HIGH V
TRIP
voltage) 20 mV
t
PURST
Power-up Reset Time Out 100 200 280 ms
t
RPD
(5)
V
CC
Detect to Reset/Output 500 ns
t
F
(5)
V
CC
Fall Time 100 µs
t
R
(5)
V
CC
Rise Time 100 µs
V
RVALID
Reset Valid V
CC
1V
NOTES:
5. This parameter is periodically sampled and not 100% tested.
6. Typical values not tested.
RESET/RESET Output Timing
SYMBOL PARAMETER MIN TYP MAX UNIT
t
WDO
Watchdog Time Out Period,
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
100
450
1
200
600
1.4
300
800
2
ms
ms
sec
t
CST
CS Pulse Width to Reset the Watchdog 400 ns
t
RST
Reset Time Out 100 200 300 ms
CS/WDI
t
CST
RESET
t
WDO
t
RST
RESET
t
WDO
t
RST
FIGURE 12. CS/WDI VS. RESET/RESET TIMING
X5163, X5165
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

X5163S8Z-2.7A

Mfr. #:
Buy X5163S8Z-2.7A
Manufacturer:
Renesas / Intersil
Description:
Supervisory Circuits CPU SUP/WDT 16K
Lifecycle:
New from this manufacturer.
Delivery:
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