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591UA-ADG

P1-P3P4-P6P7-P9P10-P12
Rev. 1.0 8/11 Copyright © 2011 by Silicon Laboratories Si590/591
Si590/591
1 ps MAX JITTER CRYSTAL OSCILLATOR (XO)
(10 MH
Z TO 810 MHZ)
Features
Applications
Description
The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry
to provide a low jitter clock at high frequencies. The Si590/591 supports any
frequency from 10 to 810 MHz. Unlike a traditional XO, where a unique
crystal is required for each output frequency, the Si590/591 uses one fixed
crystal to provide a wide range of output frequencies. This IC based
approach allows the crystal resonator to provide exceptional frequency
stability and reliability. In addition, DSPLL clock synthesis provides superior
supply noise rejection, simplifying the task of generating low jitter clocks in
noisy environments typically found in communication systems. The
Si590/591 IC based XO is factory configurable for a wide variety of user
specifications including frequency, supply voltage, output format, and
stability. Specific configurations are factory programmed at time of shipment,
thereby eliminating long lead times associated with custom oscillators.
Functional Block Diagram
Available with any-frequency output
frequencies from 10 to 810 MHz
3rd generation DSPLL
®
with superior
jitter performance: 1 ps max jitter
Better frequency stability than SAW-
based oscillators
Internal fundamental mode crystal
ensures high reliability
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
–40 to +85 ºC operating
temperature range
SONET/SDH (OC-3/12/48)
Networking
SD/HD SDI/3G SDI video
Test and measurement
Storage
FPGA/ASIC clock generation
Fixed
Frequency
XO
Any-rate
10–810 MHz
DSPLL
®
Clock
Synthesis
V
DD
CLK+CLK–
GND
OE
17 k *
17 k *
*Note: Output Enable High/Low Options Available – See Ordering Information
Ordering Information:
See page 7.
Pin Assignments:
See page 6.
(Top View)
Si5602
1
2
3
6
5
4GND
OE
V
DD
CLK+
CLK–
NC
1
2
3
6
5
4GND
NC
V
DD
CLK
NC
OE
1
2
3
6
5
4GND
NC
V
DD
CLK+
CLK–
OE
Si590 (LVDS/LVPECL/CML)
Si590 (CMOS)
Si591 (LVDS/LVPECL/CML)
Si590/591
2 Rev. 1.0
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol Test Condition Min Typ Max Units
Supply Voltage
1
V
DD
3.3 V option 2.97 3.3 3.63
V2.5 V option 2.25 2.5 2.75
1.8 V option 1.71 1.8 1.89
Supply Current I
DD
Output enabled
LVPECL
CML
LVDS
CMOS
—
—
—
—
110
100
90
80
125
110
100
90
mA
Tristate mode — 60 75
Output Enable (OE)
2
V
IH
0.75 x V
DD
——
V
V
IL
——0.5
Operating Temperature Range T
A
–40 — 85 ºC
Notes:
1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details.
2. OE pin includes an internal 17 k pullup resistor to V
DD
for output enable active high or a 17 k pull-down resistor to
GND for output enable active low. See 3. "Ordering Information" on page 7.
Table 2. CLK± Output Frequency Characteristics
Parameter
Symbol Test Condition Min Typ Max Units
Nominal Frequency
1,2
f
O
LVPECL/LVDS/CML
10 — 810
MHz
CMOS
10 — 160
Initial Accuracy
f
i
Measured at +25 °C at time of
shipping
— ±1.5 — ppm
Total Stability
Note 3, second option code “D” — — ±20 ppm
Note 3, second option code “C” — — ±30 ppm
Note 4, second option code “B” — — ±50 ppm
Note 4, second option code “A” — — ±100 ppm
Temperature Stability second option code “D” — — ±7 ppm
second option code “C” — — ±20 ppm
second option code “B” — — ±25 ppm
second option code “A” — — ±50 ppm
Powerup Time
5
t
OSC
——10ms
Notes:
1. See Section 3. "Ordering Information" on page 7 for further details.
2. Specified at time of order by part number.
3. Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 10 years aging at 40 °C. See
3. "Ordering Information" on page 7.
4. Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 15 years aging at 70 °C. See
3. "Ordering Information" on page 7.
5. Time from powerup or tristate mode to f
O
.
Si590/591
Rev. 1.0 3
Table 3. CLK± Output Levels and Symmetry
Parameter
Symbol Test Condition Min Typ Max Units
LVPECL Output Option
1
V
O
mid-level V
DD
– 1.42 — V
DD
– 1.25 V
V
OD
swing (diff) 1.1
—
1.9 V
PP
V
SE
swing (single-ended) 0.55
—
0.95 V
PP
LVDS Output Option
2
V
O
mid-level
1.125 1.20 1.275 V
V
OD
swing (diff)
0.5 0.7 0.9 V
PP
CML Output Option
2
V
O
2.5/3.3 V option mid-level — V
DD
– 1.30 —
V
1.8 V option mid-level — V
DD
– 0.36 —
V
OD
2.5/3.3 V option swing (diff) 1.10 1.50 1.90
V
PP
1.8 V option swing (diff) 0.35 0.425 0.50
CMOS Output Option
3
V
OH
0.8 x V
DD
—
V
DD
V
V
OL
——0.4
Rise/Fall time (20/80%)
t
R,
t
F
LVPECL/LVDS/CML — — 350 ps
CMOS with C
L
=15pF — 2 — ns
Symmetry (duty cycle) SYM LVPECL: V
DD
– 1.3 V (diff)
LVDS: 1.25 V (diff)
CMOS: V
DD
/2
45 — 55 %
Notes:
1. 50 to V
DD
– 2.0 V.
2. R
term
= 100 (differential).
3. C
L
= 15 pF. Sinking or sourcing 12 mA for V
DD
= 3.3V, 6mA for V
DD
= 2.5V, 3mA for V
DD
= 1.8 V.
Table 4. CLK± Output Phase Jitter
Parameter Symbol Test Condition Min Typ Max Units
Phase Jitter (RMS)
1
for 50 MHz < F
OUT
< 810 MHz
(LVPECL/LVDS/CML)
J
12 kHz to 20 MHz — 0.5 1.0 ps
Phase Jitter (RMS)
1
(LVPECL/LVDS/CML)
J
12 kHz to 20 MHz,
155.52 MHz output frequency
—0.40.7ps
Phase Jitter (RMS)
2
for 50 MHz < F
OUT
< 160 MHz
(CMOS)
J
12 kHz to 20 MHz — 0.6 1.0 ps
Notes:
1. Refer to AN256 for further information.
2. Single-ended CMOS output phase jitter measured using 33 series termination into 50 phase noise test equipment.
3.3 V supply voltage option only.
P1-P3P4-P6P7-P9P10-P12

591UA-ADG

Mfr. #:
Buy 591UA-ADG
Manufacturer:
Silicon Labs
Description:
XTAL OSC PROG XO CML 2.5V 50PPM
Lifecycle:
New from this manufacturer.
Delivery:
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