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LTC1065IN8#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
4
LTC1065
1065fb
INPUT FREQUENCY (kHz)
1
GAIN (dB)
10
100
1065 G06
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
200
A
B C
A. f
CLK
= 1MHz
B. f
CLK
= 2MHz
C. f
CLK
= 3MHz
D. f
CLK
= 4MHz
E. f
CLK
= 5MHz
V
IN
= 1.4V
RMS
T
A
= 25°C
E
D
INPUT FREQUENCY (kHz)
1
GAIN (dB)
10
100
1065 G05
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
200
A
B C
D
A. f
CLK
= 1MHz
B. f
CLK
= 2MHz
C. f
CLK
= 3MHz
D. f
CLK
= 4MHz
V
IN
= 1.4V
RMS
T
A
= 25°C
INPUT FREQUENCY (kHz)
1
GAIN (dB)
10
100
1065 G04
B C
V
IN
= 750mV
RMS
T
A
= 25°C
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
200
A
A. f
CLK
= 0.5MHz
B. f
CLK
= 1MHz
C. f
CLK
= 2MHz
E
LECTR
IC
AL C CHARA TERIST
ICS
Output Offset vs Clock,
Medium Clock RatesSelf-Clocking Frequency vs R
Output Offset vs Clock,
Low Clock Rates
EXTERNAL CLOCK FREQUENCY (kHz)
OUTPUT OFFSET (mV)
5
4
3
2
1
0
–1
–2
–3
–4
–5
1065 G03
500
1000
0
V
S
= ±7.5V
V
S
= ±5V
V
S
= ±2.5V
FREQUENCY (kHz)
R PINS 4 TO 5 (kΩ)
110
100
90
80
70
60
50
40
30
20
10
1065 G01
100 300
500
LTC1065
R
C
4
5
C = 200pF
f
OSC
≅ 1/RC
Gain vs Frequency; V
S
= ±7.5VGain vs Frequency; V
S
= ±2.5V Gain vs Frequency; V
S
= ±5V
CCHARA TERIST
ICS
UW
AT
Y
P
I
CA
LPER
F
O
R
C
E
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The maximum clock frequency is arbitrarily defined as the
frequency at which the filter AC response exhibits ≥ 1dB of gain peaking.
Note 3: At limited temperature ranges (i.e., T
A
≤ 50°C) the minimum clock
frequency can be as low as 10Hz. The typical minimum clock frequency is
arbitrarily defined as the clock frequency at which the output DC offset
changes by more than 1mV.
Note 4: The wideband noise specification does not include the clock
feedthrough.
Note 5: To properly evaluate the filter’s harmonic distortion an inverting
output buffer is recommended. An output buffer (although recommended)
is not necessarily needed when measuring output DC offset or wideband
noise (see Figure 3).
Note 6: The output DC offset is optimized for ±5V supply. The output DC
offset shifts when the power supplies change; however, this phenomenon
is repeatable and predictable.
Note 7: The LTC1065C is guaranteed to meet the specified performance
from 0°C to 70°C and is designed, characterized and expected to meet
specified performance from –40°C to 85°C but is not tested or QA
sampled at these temperatures. The LTC1065I is guaranteed to meet
specified performance from –40°C to 85°C.
EXTERNAL CLOCK FREQUENCY (Hz)
OUTPUT OFFSET (mV)
50
45
40
35
30
25
20
15
10
5
0
1065 G02
10
110
210
A
B
A. T
A
= 25°C
B. T
A
= 85°C
V
S
= ±5V
5
LTC1065
1065fb
TOTAL POWER SUPPLY VOLTAGE (V)
0
POWER SUPPLY CURRENT (mA)
15
12
9
6
3
0
16
1065 G15
4
8
12
20
6
10
14
18
2
–40°C
85°C
25°C
INPUT FREQUENCY (kHz)
0
PHASE MISMATCH (±DEG)
0.6
0.5
0.4
0.3
0.2
0.1
0
4
81216
1065 G14
20 2426
10
14 18 22
V
S
= ± 7.5V
V
IN
= 1V
RMS
f
C
= 20kHz
f
CLK
= 2MHz
INPUT FREQUENCY (Hz)
100
PASSBAND GAIN (dB)
1
0
–1
–2
–3
–4
–5
–6
1k 10k 100k
1065 G13
40
0
–40
–80
–120
–160
–200
–240
PHASE (DEG)
±2.5V ≤ V
S
≤ ±7.5V, T
A
= 25°C
B
A
A
B
PHASE PHASE
f
C
=1kHz
f
CLK
=100kHz
f
C
=10kHz
f
CLK
=1MHz
INPUT (V
RMS
)
0.1
0.001
THD + NOISE (%)
15
1065 G11
0.01
0.1
1
A
B
f
IN
= 1kHz
T
A
= 25°C
A. f
C
= 10kHz, f
CLK
= 1MHz
B. f
C
= 20kHz, f
CLK
= 2MHz
FREQUENCY (kHz)
1
0.001
THD (%)
0.01
0.1
1
10
1065 G12
5
V
IN
= 2.5V
RMS
, S/N = 90dB
f
C
= 10kHz, f
CLK
= 1MHz
T
A
= 25°C
FREQUENCY (kHz)
1
0.001
THD (%)
0.01
0.1
1
10
1065 G10
5
V
IN
= 1.5V
RMS
f
C
= 10kHz, f
CLK
= 1MHz
T
A
= 25°C
INPUT (V
RMS
)
0.1
0.001
THD + NOISE (%)
15
1065 G09
0.01
0.1
1
A
B
f
IN
= 1kHz, T
A
= 25°C
A. f
C
= 10kHz, f
CLK
= 1MHz
B. f
C
= 20kHz, f
CLK
= 2MHz
FREQUENCY (kHz)
1
0.001
THD (%)
0.01
0.1
1
2
1065 G08
3 4
5
V
IN
= 0.75V
RMS
,
S/N = 80dB
f
C
= 5kHz, f
CLK
= 500kHz
T
A
= 25°C
INPUT (V
RMS
)
0.1
0.001
THD + NOISE (%)
15
1065 G07
0.01
0.1
1
A
B
f
IN
= 1kHz, T
A
= 25°C
A. f
C
= 5kHz, f
CLK
= 0.5MHz
B. f
C
= 10kHz, f
CLK
= 1MHz
Passband Gain and Phase
vs Input Frequency
Power Supply Current vs
Power Supply Voltage
CCHARA TERIST
ICS
UW
AT
Y
P
I
CA
LPER
F
O
R
C
E
THD + Noise vs Input Voltage;
V
S
= Single 5V, AGND = 2V
THD vs Frequency;
V
S
= Single 5V, AGND = 2V
THD + Noise vs Input Voltage;
V
S
= ±7.5V
THD vs Frequency; V
S
= ±5V
Typical Phase Matching
Device to Device
THD vs Frequency;
V
S
= ±7.5V
THD + Noise vs Input Voltage;
V
S
= ±5V
6
LTC1065
1065fb
INPUT FREQUENCY (kHz)
0
GROUP DELAY (µs)
45
40
35
30
25
20
15
10
5
0
621
3
91815
12
V
S
= ±5V
f
C
= 10kHz
1065 G17
CCHARA TERIST
ICS
UW
AT
Y
P
I
CA
LPER
F
O
R
C
E
HORIZONTAL: 0.1ms/DIV, VERTICAL: 2V/DIV
V
S
= ±5V, f
C
= 10kHz, V
IN
= 1kHz ±3V
P
SQUARE WAVE
1065 G16
Transient Response Group Delay
PI FU CTIO S
U
UU
Power Supply Pins (Pins 6, 3, N Package)
The positive and negative supply pin should be bypassed
with a high quality 0.1µF ceramic capacitor. In applications
where the clock pin (5) is externally swept to provide
several cutoff frequencies, the output DC offset variation
is minimized by connecting an additional 1µF solid tanta-
lum capacitor in parallel with the 0.1µF disc ceramic. This
technique was used to generate the graphs of the output
DC offset variation versus clock; they are illustrated in the
Typical Performance Characteristics section.
When the power supply voltage exceeds ±7V, and when
V
–
is applied before V
+
(if V
+
is allowed to go below
ground) connect a signal diode between the positive
supply pin and ground to prevent latch-up (see Typical
Applications).
Ground Pin (Pin 2, N Package)
The ground pin merges the internal analog and digital
ground paths. The potential of the ground pin is the
reference for the internal switched-capacitor resistors,
and the reference for the external clock. The positive input
of the internal op amp is also tied to the ground pin.
For dual supply operation, the ground pin should be
connected to a high quality AC and DC ground. A ground
plane, if possible, should be used. A poor ground will
degrade DC offset and it will increase clock feedthrough,
noise and distortion.
A small amount of AC current flows out of the ground pin
whether or not the internal oscillator is used. The fre-
quency of the ground current equals the frequency of the
clock. The average value of this current is approximately
55µA, 110µA, 170µA for ±2.5V, ±5V and ±7.5V supplies
respectively.
For single supply operation, the ground pin should be
preferably biased at half supply (see Typical Applications).
V
OS
Adjust Pin (Pin 8, N Package)
The V
OS
adjust pin can be used to trim any small amount
of output DC offset voltage or to introduce a desired output
DC level. The DC gain from the V
OS
adjust pin to the filter
output pin equals two.
Any DC voltage applied to this pin will reflect at the output
pin of the filter multiplied by two.
If the V
OS
adjust pin is not used, it should be shorted to the
ground pin. The DC bias current flowing into the V
OS
adjust
pin is typically 10pA.
The V
OS
adjust pin should always be connected to an AC
ground; AC signals applied to this pin will degrade the filter
response.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

LTC1065IN8#PBF

Mfr. #:
Buy LTC1065IN8#PBF
Manufacturer:
Analog Devices Inc.
Description:
Active Filter V Low Offset Clk Sweep Bessel Filter
Lifecycle:
New from this manufacturer.
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