7
LTC1065
1065fb
CLOCK FREQUENCY (MHz)
1
MAXIMUM LOAD CAPACITANCE (pF )
200
180
160
140
120
100
80
60
40
20
0
310
1065 F02
245
6
78
9
V
S
= ±2.5V
V
S
= ±5V
V
S
= ±7.5V
T
A
= 25°C
PI FU CTIO S
U
UU
Input Pin (Pin 1, N Package)
Pin 1 is the filter input and it is connected to an internal
switched-capacitor resistor. If the input pin is left floating,
the filter output will saturate. The DC input impedance of
pin 1 is very high; with ±5V supplies and 1MHz clock, the
DC input impedance is typically 1GΩ. A resistor R
IN
in
series with the input pin will not alter the value of the filter’s
DC output offset (Figure 1). R
IN
should however, be limited
to a maximum value (Table 1), otherwise the filter’s pass-
band will be affected. Refer to the Applications Information
section for more details.
V
IN
V
OUT
1065 F01
V
–
V
+
R
IN
1
2
3
4
8
7
6
5
LTC1065
f
CLK
Figure 1.
Table 1. R
IN(MAX)
vs Clock and Power Supply
R
IN(MAX)
V
S
= ±7.5V V
S
= ±5V V
S
= ±2.5V
f
CLK
= 4MHz 1.82k – –
f
CLK
= 3MHz 3.01k 2.49k –
f
CLK
= 2MHz 4.32k 3.65k 2.37k
f
CLK
= 1MHz 9.09k 8.25k 7.5k
f
CLK
= 500kHz 17.8k 16.9k 16.9k
f
CLK
= 100kHz 95.3k 90.9k 90.9k
100:1. The high (V
HIGH
) and low (V
LOW
) clock logic
threshold levels are illustrated in Table 2. Square wave
clocks with duty cycles between 30% and 50% are strongly
recommended. Sinewave clocks are not recommended.
Output Pin (Pin 7, N Package)
Pin 7 is the filter output. This pin can typically source over
20mA and sink 2mA. Pin 7 should not drive long coax
cables, otherwise the filter’s total harmonic distortion will
degrade. The maximum load the filter output can drive and
still maintain the distortion levels, shown in the Typical
Performance Characteristics, is 20k.
Clock Input Pin (Pin 5, N Package)
An external clock, when applied to pin 5, tunes the filter
cutoff frequency. The clock-to-cutoff frequency ratio is
Table 2. Clock Pin Threshold Levels
POWER SUPPLY V
HIGH
V
LOW
V
S
= ±2.5V 1.5V 0.5V
V
S
= ±5V 3V 1V
V
S
= ±7.5V 4.5V 1.5V
V
S
= ±8V 4.8V 1.6V
V
S
= 5V, 0V 4V 3V
V
S
= 12V, 0V 9.6V 7.2V
V
S
=15V, 0V 12V 9V
Clock Output Pin (Pin 4, N Package)
Any external clock applied to the clock input pin appears
at the clock output pin. The duty cycle of the clock output
equals the duty cycle of the external clock applied to the
clock input pin. The clock output pin swings to the power
supply rails. When the LTC1065 is used in a self-clocking
mode, the clock of the internal oscillator appears at the
clock output pin with a 30% duty cycle. The clock output
pin can be used to drive other LTC1065s or other ICs. The
maximum capacitance, C
L(MAX)
, the clock output pin can
drive is illustrated in Figure 2.
Figure 2. Maximum Load Capacitance at the Clock Output Pin
