MAX9390/MAX9391
Anything-to-LVDS Dual 2 x 2
Crosspoint Switches
_______________________________________________________________________________________ 7
t
PHL
t
PLH
80%
20%
20%
80%
50% V
OD
= 0
V
OD
= 0
V
ID
= 0
V
OD
= 0
V
OD
= 0
V
ID
= 0
50%
V
ID
= V
IN_ _
- V
IN_ _
V
OD
= V
OUT_ _
- V
OUT_ _
t
PLH
AND t
PHL
MEASURED FOR ANY COMBINATION OF _SEL0 AND _SEL1.
V
IN_ _
V
IHD
V
ILD
V
IN_ _
V
OUT_ _
V
OUT_ _
t
F
t
R
V
IHD
V
ILD
V
IHD
V
ILD
V
IH
V
IL
V
OD
= 0
t
SWITCH
t
SWITCH
IN_0
IN_0
IN_1
IN_1
V
ID
= 0
V
ID
= 0
_SEL_
1.5V
IN_1
OUT_ _
OUT_ _
EN_0 = EN_1 = HIGH
V
ID
= V
IN_ _
- V
IN_ _
IN_0 IN_0
1.5V
V
OD
= 0
V
ID
= V
IN_ _
- V
IN_ _
ΔV
OD
= V
OD
- V
OD
*
ΔV
OS
= V
OS
- V
OS
*
V
OD
AND V
OS
ARE MEASURED WITH V
ID
= +100mV
V
OD
* AND V
OS
*
ARE MEASURED WITH V
ID
= -100mV
IN_ _
IN_ _
R
L
/2
R
L
/2
V
OD
OUT_ _
OUT_ _
1/4 MAX9390/MAX9391
EN_ _ = HIGH
V
OS
Figure 1. Output Transition Time and Propagation Delay Timing
Diagram
Figure 3. Input to Rising/Falling Edge Select and Mux Switch Timing Diagram
Figure 2. Test Circuit for V
OD
and V
OS
MAX9390/MAX9391
Anything-to-LVDS Dual 2 x 2
Crosspoint Switches
8 _______________________________________________________________________________________
V
ID
= V
IN_ _
- V
IN_ _
0
3V
1.5V
1.5V
V
EN_ _
t
PHD
t
PHD
t
PDH
t
PDH
50%
50%
50%
50%
V
OUT_ _
WHEN V
ID
= +100mV
V
OUT_ _
WHEN V
ID
= -100mV
C
L
PULSE
GENERATOR
IN_ _
IN_ _
R
L
/2
R
L
/2
50Ω
OUT_ _
OUT_ _
1.25V
C
L
1/4 MAX9390/MAX9391
V
OUT_ _
WHEN V
ID
= -100mV
V
OUT_ _
WHEN V
ID
= +100mV
R
L
= 100Ω ±1%
C
L
= 1.0pF
_SEL0
_SEL1
0
1
0
1
IN_1
IN_1
PULSE
GENERATOR
OUT_0
OUT_0
OUT_1
OUT_1
C
L
R
L
R
L
IN_0
IN_0
50Ω
C
L
50Ω
C
L
C
L
MAX9390
MAX9391
EN_0 = EN_1 = HIGH
1 CHANNEL SHOWN
R
L
= 100Ω ±1%
C
L
= 1.0pF
Figure 4. Output Active-to-Disable and Disable-to-Active Test Circuit and Timing Diagram
Figure 5. Output Transition Time, Propagation Delay, and Output Channel-to-Channel Skew Test Circuit
MAX9390/MAX9391
Anything-to-LVDS Dual 2 x 2
Crosspoint Switches
_______________________________________________________________________________________ 9
Detailed Description
The LVDS interface standard provides a signaling
method for point-to-point communication over a con-
trolled-impedance medium as defined by the ANSI
TIA/EIA-644 standard. LVDS utilizes a lower voltage
swing than other communication standards, achieving
higher data rates with reduced power consumption,
while reducing EMI emissions and system susceptibility
to noise.
The MAX9390/MAX9391 1.5GHz dual 2 x 2 crosspoint
switches optimize high-speed, low-power, point-to-
point interfaces. The MAX9390 accepts LVDS and
HSTL signals, while the MAX9391 accepts LVPECL and
CML signals. Both devices route the input signals to
either or both LVDS outputs.
When configured as a 1:2 splitter, the outputs repeat
the selected inputs. This configuration creates copies
of signals for protection switching. When configured as
a repeater, the device operates as a two-channel
buffer. Repeating restores signal amplitude, allowing
isolation of media segments or longer media drive.
When configured as a 2:1 mux, select primary or back-
up signals to provide a protection-switched, fault-toler-
ant application.
Input Fail-Safe
The differential inputs of the MAX9390/MAX9391 pos-
sess internal fail-safe protection. Fail-safe circuitry
forces the outputs to a differential low condition for
undriven inputs or when the common-mode voltage
exceeds the specified range. The MAX9390 provides
high-level input fail-safe detection for LVDS, HSTL, and
other GND-referenced differential inputs. The MAX9391
provides low-level input fail-safe detection for LVPECL,
CML, and other V
CC
-referenced differential inputs.
Select Function
The _SEL_ logic inputs control the input and output sig-
nal connections. Two logic inputs control the signal rout-
ing for each channel. _SEL0 and _SEL1 allow the
devices to be configured as a differential crosspoint
switch, 2:1 mux, dual repeater, or 1:2 splitter (Figure 7).
See Table 1 for mode-selection settings (insert A or B for
the _). Channels A and B possess separate select
inputs, allowing different configurations for each channel.
Enable Function
The EN_ _ logic inputs enable and disable each set of
differential outputs. Connect EN_0 to V
CC
to enable the
OUT_0/OUT_0 differential output pair. Connect EN_0 to
GND to disable the OUT_0/OUT_0 differential output
pair. The differential output pairs assert to a differential
low condition when disabled.
V
OD
= V
OUT_ _
- V
OUT_ _
V
OD
= 0
t
CCS
V
OD
= 0
V
OD
= 0 V
OD
= 0
t
CCS
V
OUT_0
V
OUT_0
V
OUT_1
V
OUT_1
t
CCS
MEASURED WITH _SEL0 = _SEL1 = HIGH OR LOW
(1:2 SPLITTER CONFIGURATION).
Figure 6. Output Channel-to-Channel Skew
OUT_0
OUT_0 OR OUT_1
OUT_1
2 x 2 CROSSPOINT
2:1 MUX
1:2 SPLITTER
DUAL REPEATER
OUT_0
OUT_1
OUT_0
OUT_1
IN_0
IN_1
IN_0
IN_1
IN_0
IN_1
IN_0 OR IN_1
Figure 7. Programmable Configurations

MAX9390EHJ+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog & Digital Crosspoint ICs X-to-LVDS Dual 2x2 Crosspoint Swtch
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet