CY62167DV30 MoBL
®
Document #: 38-05328 Rev. *G Page 5 of 12
Data Retention Waveform
[14]
Switching Characteristics Over the Operating Range
[15]
Parameter Description
45 ns
[12]
55 ns 70 ns
UnitMin. Max. Min. Max. Min. Max.
Read Cycle
t
RC
Read Cycle Time 45 55 70 ns
t
AA
Address to Data Valid 45 55 70 ns
t
OHA
Data Hold from Address Change 10 10 10 ns
t
ACE
CE
1
LOW and CE
2
HIGH to Data Valid 45 55 70 ns
t
DOE
OE LOW to Data Valid 25 25 35 ns
t
LZOE
OE LOW to LOW Z
[16]
555 ns
t
HZOE
OE HIGH to High Z
[16, 17]
15 20 25 ns
t
LZCE
CE
1
LOW and CE
2
HIGH to Low Z
[16]
10 10 10 ns
t
HZCE
CE
1
HIGH and CE
2
LOW to High Z
[16, 17]
20 20 25 ns
t
PU
CE
1
LOW and CE
2
HIGH to Power-up 0 0 0 ns
t
PD
CE
1
HIGH and CE
2
LOW to Power-down 45 55 70 ns
t
DBE
BLE/BHE LOW to Data Valid 45 55 70 ns
t
LZBE
BLE/BHE LOW to Low Z
[16]
10 10 10 ns
t
HZBE
BLE/BHE HIGH to HIGH Z
[16, 17]
15 20 25 ns
Write Cycle
[18]
t
WC
Write Cycle Time 45 55 70 ns
t
SCE
CE
1
LOW and CE
2
HIGH
to Write End 40 40 60 ns
t
AW
Address Set-Up to Write End 40 40 60 ns
t
HA
Address Hold from Write End 0 0 0 ns
t
SA
Address Set-Up to Write Start 0 0 0 ns
t
PWE
WE Pulse Width 35 40 45 ns
t
BW
BLE/BHE LOW to Write End 40 40 60 ns
t
SD
Data Set-Up to Write End 25 25 30 ns
t
HD
Data Hold from Write End 0 0 0 ns
t
HZWE
WE LOW to High-Z
[16, 17]
15 20 25 ns
t
LZWE
WE HIGH to Low-Z
[16]
10 10 10 ns
Notes:
14. BHE
.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
15.Test conditions for all parameters other than Tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of V
CC(typ)
/2, input pulse levels
of 0 to V
CC(typ.)
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads and Waveforms” section.
16.At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device.
17. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
18.The internal Write time of the memory is defined by the overlap of WE
, CE
1
= V
IL
, BHE and/or BLE = V
IL
, and CE
2
= V
IH
. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the Write.
V
CC
, min.
V
CC
, min.
t
CDR
V
DR
>
1.5 V
DATA RETENTION MODE
t
R
CE
1
or
V
CC
BHE,BLE
or
CE
2
