BD3814FV-E2 Datasheet BD3814FV-E2 | P4-P6

Technical Note

4/10

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2010.06 - Rev.A

BD3814FV

●Timing chart

1. Signal timing conditions

・Data is read on the rising edge of the clock.

・Latch is read on the falling edge of the clock.

・Latch signal must terminate with the LOW state.

* To avoid malfunctions, clock and data signals must terminate with the LOW state.

Fig.1

Parameter Symbol

Limits

Unit

Min. Typ. Max.

Minimum clock width twc 2.0 －－ μs

Minimum data width twd 2.0 －－ μs

Minimum latch width twl 2.0 －－ μs

LOW hold width twh 2.0 －－ μs

Data setup time (DATA→CLK) tsd 1.0 －－ μs

Data hold time (CLK→DATA) thd 1.0 －－ μs

Latch setup time (CLK→LATCH) tsl 1.0 －－ μs

Latch hold time (DATA→LATCH) thl 1.0 －－ μs

Latch low setup time ts 1.0 －－ μs

Latch low hold time th 1.0 －－ μs

2. Voltage conditions for control signal

Parameter

Condition

Limits

Unit

Min. Typ. Max.(≦Vcc)

“H” input voltage

Vcc=5 ~ 7.3V

VEE=-5 ~ -7.3V

2.2 － 5.5 V

“L” input voltage 0 － 1.0 V

CL

(CLOCK)

DA

DATA

LATCH

thd thdth ts tsl thl tsd

twc

twh

twd

twl

DATA DATA

LATCH

90% 90% 90% 90%

10% 10% 10%

90% 90% 90%

90% 90%

10%

10% 10%

twc

Terminate

with Low.

Technical Note

5/10

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2010.06 - Rev.A

BD3814FV

3. Basic configuration of control data format

Data input direction

MSB LSB

Data

D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Data Select Address

・Control data format

Data input direction

Select Address

Data

①

D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Treble Bass Tone * * * * * 0 0 0

Data

②

D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Master Volume FRch Master Volume FLch 0 0 1

Data

③

D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Master Volume SRch Master Volume SLch 0 1 0

Data

④

D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Master Volume Cch Master Volume SWch 0 1 1

By changing select address, 4 control data formats can be selected.

Do not set the select address data to any format other than that specified above.

At power-on sequence, initialize all data.

* is 0 or 1.

Example:

Data input direction

MSB LSB MSB LSB MSB LSB MSB LSB

Data① L Data② L Data③ LData④ L

“L” shows latch.

After power-on, for the second and subsequent times, only the necessary data can be selected for setting

Example: When to change bus,

Input direction

MSB LSB

Data① L

“L” shows latch.

Technical Note

6/10

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2010.06 - Rev.A

BD3814FV

●Application circuit

UNIT

RESISTOR: Ω

CAPACITOR: F

Fig.2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

10

µ

IN

SW

10

µ

IN

SR

10

µ

IN

SL

10

µ

IN

C

0.1

µ

0.1

µ

CL

DA

MUTE

10K

MASTER

VOLUME

0

～

-95dB

1dB/step

，

MUTE

OUTSW

BASS

TREBLE

OUTSR

OUTSL

OUTC

OUTFR

OUTFL

0.1

µ

0.1

µ

4.7K

4700P

10

µ

IN

FL

10

µ

IN

FR

47K

4700P

Vcc

47

µ

VEE

47

µ

Ri=20K

BD3814FV-E2

BD3814FV-E2

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