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AD7541AKP-REEL

P1-P3P4-P6P7-P9P10-P12P13-P14
AD7541A Data Sheet
Rev. C | Page 6 of 13
PIN CONFIGURATIONS
AD7541A
TOP VIEW
(Not to Scale)
OUT 1
1
R
FEEDBACK
18
OUT 2
2
V
REF
IN
17
GND
3
V
DD
(+)
16
BIT 1 (MSB)
4
BIT 12 (LSB)
15
BIT 2
5
BIT 11
14
BIT 3
6
BIT 10
13
BIT 4
7
BIT 8
12
BIT 5
8
BIT 8
11
BIT 6
9
BIT 7
10
00718-002
Figure 2. 18-Lead PDIP and 18-Lead SOIC Pin Configuration
4
GND
5
BIT 1 (MSB)
6
BIT 2
7
BIT 3
8
BIT 4
18
V
DD
17
BIT 12 (LSB)
16
BIT 11
15
BIT 10
14
BIT 9
19
V
REF
20
R
FEEDBACK
1
NC
2
OUT 1
3
OUT 2
13
BIT 8
12
BIT 7
11
NC
10
BIT 6
9
BIT 5
AD7541A
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT.
00718-003
Figure 3. 20-Lead PLCC Pin Configuration
Data Sheet AD7541A
Rev. C | Page 7 of 13
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero scale and full scale, and it is expressed in % of
full-scale range or (sub) multiples of 1 LSB.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal l LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
over the operating temperature range ensures monotonicity.
Gain Error
Gain error is a measure of the output error between an ideal
DAC and the actual device output. For the AD7541A, ideal
maximum output is
−(4095/4096)(V
REF
)
Gain error is adjustable to zero using external trims, as shown
in Figure 7, Figure 8, and Figure 9.
Output Leakage Current
Current that appears at OUT I with the DAC loaded to all 0s or
at OUT 2 with the DAC loaded to all 1s.
Multiplying Feedthrough Error
AC error due to capacitive feedthrough from the V
REF
terminal
to OUT 1 with the DAC loaded to all 0s.
Output Current Settling Time
Time required for the output function of the DAC to settle to
within 1/2 LSB for a given digital input stimulus, that is, 0 to
full scale.
Propagation Delay
The propagation delay is a measure of the internal delay of the
circuit, and it is measured from the time a digital input changes
to the point at which the analog output at OUT 1 reaches 90%
of its final value.
Digital-to-Analog Glitch Impulse (QDA)
The QDA is a measure of the amount of charge injected from
the digital inputs to the analog outputs when the inputs change
state. It is usually specified as the area of the glitch in nV-sec
and is measured with V
REF
= GND and a Model 50K as the
output op amp, C1 (phase compensation) = 0 pF.
AD7541A Data Sheet
Rev. C | Page 8 of 13
THEORY OF OPERATION
The simplified digital-to-analog circuit is shown in Figure 4. An
inverted R-2R ladder structure was used, meaning the binarily
weighted currents are switched between the OUT 1 and OUT 2
bus lines, thus maintaining a constant current in each ladder leg
independent of the switch state.
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
LOGIC: A SWITCH IS CLOSED TO I
OUT 1
FOR
ITS DIGITAL INPUT IN A HIGH STATE.
20kΩ
S1
10kΩ
20kΩ
S2
10kΩ
20kΩ
S3
10kΩ
20kΩ
S12
20kΩ
V
REF
OUT 2
BIT 1 (MSB)
OUT 1
BIT 2 BIT 3 BIT 12 (LSB)
R
FEEDBACK
10kΩ
00718-005
Figure 4. Functional Diagram (Inputs High)
The input resistance at V
REF
(see Figure 4) is always equal to
R
LDR
, which is the R-2R ladder characteristic resistance and is
equal to value R. Because R
IN
at the V
REF
pin is constant, the
reference terminal can be driven by a reference voltage or a
reference current, ac or dc, of positive or negative polarity. If a
current source is used, a low temperature coefficient external
R
FEEDBACK
is recommended to define the scale factor.
EQUIVALENT CIRCUIT ANALYSIS
The equivalent circuits for all digital inputs low and all digital
inputs high are shown in Figure 5 and Figure 6. In Figure 5 with
all digital inputs low, the reference current is switched to OUT 2.
The current source, I
LEAKAGE
, is composed of surface and junction
leakages to the substrate, while the I/
4096
current source represents a
constant 1-bit current drain through the termination resistor on
the R-2R ladder. The on capacitance of the output N-channel
switch is 200 pF, as shown on the OUT 2 terminal. The off
switch capacitance is 70 pF, as shown on the OUT 1 terminal.
Analysis of the circuit for all digital inputs high, as shown in
Figure 5, is similar to Figure 4; however, the on switches are
now on the OUT 1 terminal; therefore, 200 pF at that terminal.
R
FEEDBACK
R
70pF
OUT 1
I
LEAKAGE
200pF
OUT 2
I
LEAKAGE
I
/4096
R
≈
15kΩ
V
REF
I
REF
00718-006
Figure 5. DAC Equivalent Circuit, All Digital Inputs Low
R
FEEDBACK
R
OUT 1
70pF
I
LEAKAGE
OUT 2
200pF
I
LEAKAGE
I
/4096
R
≈
15kΩ
V
REF
I
REF
00718-007
Figure 6. DAC Equivalent Circuit All Digital Inputs High
P1-P3P4-P6P7-P9P10-P12P13-P14

AD7541AKP-REEL

Mfr. #:
Buy AD7541AKP-REEL
Manufacturer:
Analog Devices Inc.
Description:
IC DAC 12BIT MULT MONO 20-PLCC
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