74LVC377_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 06 — 20 November 2012 6 of 15
NXP Semiconductors
74LVC377
Octal D-type flip-flop with data enable; positive-edge trigger
[1] Typical values are measured at T
amb
=25C and V
CC
= 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2] t
pd
is the same as t
PLH
and t
PHL
.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in Volts
N = number of inputs switching
(C
L
V
CC
2
f
o
) = sum of the outputs
t
h
hold time E to CP; see Figure 5
V
CC
= 1.65 V to 1.95 V 1.5 - - 1.5 - ns
V
CC
= 2.3 V to 2.7 V 0.5 - - 0.5 ns
V
CC
= 2.7 V 0.0 1.0 - 0.0 - ns
V
CC
= 3.0 V to 3.6 V 1.0 0 - 1.0 - ns
Dn to CP; see Figure 5
V
CC
= 1.65 V to 1.95 V 1.5 - - 1.5 - ns
V
CC
= 2.3 V to 2.7 V 0.5 - - 0.5 ns
V
CC
= 2.7 V 0.0 1.1 - 0.0 - ns
V
CC
= 3.0 V to 3.6 V 0.0 1.0 - 0.0 - ns
f
max
maximum
frequency
see Figure 4
V
CC
= 1.65 V to 1.95 V 80 - - 64 - MHz
V
CC
= 2.3 V to 2.7 V 100 - - 80 MHz
V
CC
= 2.7 V 150 - - 120 - MHz
V
CC
= 3.0 V to 3.6 V 150 330 - 120 - MHz
t
sk(o)
output skew time V
CC
= 3.0 V to 3.6 V
[3]
- - 1.0 - 1.5 ns
C
PD
power dissipation
capacitance
per flip-flop; V
I
= GND to V
CC
[4]
V
CC
= 1.65 V to 1.95 V - 12.1 - - - pF
V
CC
= 2.3 V to 2.7 V - 15.8 - - - pF
V
CC
= 3.0 V to 3.6 V - 19.0 - - - pF
Table 7. Dynamic characteristics
?ontinued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 6.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
74LVC377_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 06 — 20 November 2012 7 of 15
NXP Semiconductors
74LVC377
Octal D-type flip-flop with data enable; positive-edge trigger
11. Waveforms
Measurement points are given in Table 8.
Logic levels: V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 4. Propagation delay clock (CP) to output (Qn), pulse width clock (CP), and maximum frequency
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 5. Data set-up and hold times of data input (Dn) and enable input (E) and pulse width of enable input (E)
t
h
t
su
t
h
t
su
V
M
V
M
GND
V
CC
GND
V
CC
Dn input
t
su
t
W
V
M
mna921
GND
V
CC
CP input
E input
Table 8. Measurement points
Supply voltage Input Output
V
CC
V
M
V
M
1.2 V 0.5 V
CC
0.5 V
CC
1.65 V to 1.95V 0.5 V
CC
0.5 V
CC
2.3 V to 2.7 V 0.5 V
CC
0.5 V
CC
2.7V 1.5V 1.5V
3.0V to 3.6V 1.5V 1.5V
74LVC377_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 06 — 20 November 2012 8 of 15
NXP Semiconductors
74LVC377
Octal D-type flip-flop with data enable; positive-edge trigger
Test data is given in Table 9.
Definitions for test circuit:
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
Fig 6. Test circuit for switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aaf615
V
CC
V
I
V
O
DUT
C
L
R
T
R
L
PULSE
GENERATOR
Table 9. Test data
Supply voltage Input Load
V
I
t
r
, t
f
C
L
R
L
1.2 V V
CC
2 ns 30 pF 1 k
1.65 V to 1.95 V V
CC
2 ns 30 pF 1 k
2.3 V to 2.7 V V
CC
2 ns 30 pF 500
2.7V 2.7V 2.5 ns 50 pF 500
3.0Vto3.6V 2.7V 2.5 ns 50 pF 500

74LVC377PW,112

Mfr. #:
Manufacturer:
Nexperia
Description:
Flip Flops 3.3V OCTAL POS
Lifecycle:
New from this manufacturer.
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