10
I
F
(ON)
50 % I
F
(ON)
0 mA
t
PLH
t
PHL
V
OH
1.3 V
V
OL
INPUT I
F
OUTPUT
V
O
Figure 2. Typical logic high output current vs.
temperature.
Figure 3. Output voltage vs. forward input
current.
Figure 4. Typical input diode forward
characteristic.
Figure 1. Typical logic low output voltage vs.
temperature.
Notes:
1. Derate total package power dissipation, P
T
,
linearly above 70°C free air temperature at a
rate of 4.5 mW/°C.
2. Duration of output short circuit time should
not exceed 10 ms.
3. Device considered a two-terminal device:
pins 1, 2, 3, and 4 shorted together and pins
5, 6, 7, and 8 shorted together.
4. The t
PLH
propagation delay is measured
from the 50% point on the leading edge of
the input pulse to the 1.3 V point on the
leading edge of the output pulse. The t
PHL
propagation delay is measured from the
50% point on the trailing edge of the input
pulse to the 1.3 V point on the trailing edge
of the output pulse.
5. When the peaking capacitor is omitted,
propagation delay times may increase by
100 ns.
6. CM
L
is the maximum rate of rise of the
common mode voltage that can be
sustained with the output voltage in the
logic low state (V
O
< 0.8 V). CM
H
is the
maximum rate of fall of the common mode
voltage that can be sustained with the
output voltage in the logic high state
(V
O
> 2.0 V).
I
OH
– HIGH LEVEL OUTPUT CURRENT – mA
-60
-8
T
A
– TEMPERATURE – °C
100
0
-20
-5
20 60-40 0 40 80
-3
-1
-6
V
CC
= 4.5 V
I
F
= 5 mA
-7
-4
-2
V
O
= 2.7 V
V
O
= 2.4 V
I
F
– FORWARD CURRENT – mA
1.1
0.001
V
F
– FORWARD VOLTAGE – V
1.0
1000
1.3
0.01
1.51.2 1.4
0.1
T
A
= 25 °C
10
100
I
F
+
–
V
F
7. Use of a 0.1 µF bypass capacitor connected
between pins 5 and 8 is recommended.
8. In accordance with UL1577, each
optocoupler is proof tested by applying an
insulation test voltage ≥4500 V rms for one
second (leakage detection current limit, I
I-O
≤5 µA). This test is performed before the
100% production test for partial discharge
(Method b) shown in the IEC/EN/DIN EN
60747-5-2 Insulation Characteristics Table, if
applicable.
Figure 5. Test circuit for t
PLH
, t
PHL
, t
r
, and t
f
.
V
OL
– LOW LEVEL OUTPUT VOLTAGE – V
-60
0
T
A
– TEMPERATURE – °C
100
1.0
-20
0.4
20 60-40 0 40 80
0.6
0.8
0.2
V
CC
= 4.5 V
I
F
= 0 mA
V
O
= 6.4 mA
0.1
0.3
0.5
0.7
0.9
V
O
– OUTPUT VOLTAGE – V
0
0
I
F
– INPUT CURRENT – mA
2.0
5
2
1.00.5
3
1
4
I
OL
= 6.4 mA
I
OH
= -2.6 mA
1.5
V
CC
= 4.5 V
T
A
= 25 °C
7
1
4
5
6
8
HCPL-2200
GND
V
CC
5 V
619 Ω
INPUT
MONITORING
NODE
PULSE GEN.
t
r
= t
f
=
5 ns
f = 100 kHz
10 % DUTY
CYCLE
V
O
= 5 V
C
2
=
15 pF
THE PROBE AND JIG CAPACITANCES
ARE INCLUDED IN C
1
AND
C
2
.
OUTPUT V
O
MONITORING
NODE
V
CC
R
1
D
1
D
2
5 kΩ
D
3
D
4
2
3
C
1
=
120 pF
R
I
I
F
(ON)
2.15 kΩ
1.6 mA
1.10 kΩ
3 mA
681 Ω
5 mA
ALL DIODES ARE 1N916 OR 1N3064.
I
F
