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74ACT843SCX

P1-P3P4-P6
© 2000 Fairchild Semiconductor Corporation DS009800 www.fairchildsemi.com
July 1988
Revised September 2000
74ACT843 9-Bit Transparent Latch
74ACT843
9-Bit Transparent Latch
General Description
The ACT843 bus interface latch is designed to eliminate
the extra packages required to buffer existing latches and
provide extra data width for wider address/data paths.
Features
■ TTL compatible inputs
■ 3-STATE outputs for bus interfacing
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (SPC not available in Tape and Reel.)
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation
Order Number Package Number Package Description
74ACT843SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACT843SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
D
0
–D
8
Data Inputs
O
0
–O
8
Data Outputs
OE
Output Enable
LE Latch Enable
CLR
Clear
PRE
Preset
www.fairchildsemi.com 2
74ACT843
Functional Description
The ACT843 consists of nine D-type latches with 3-STATE
outputs. The flip-flops appear transparent to the data when
Latch Enable (LE) is HIGH. This allows asynchronous
operation, as the output transition follows the data in transi-
tion. On the LE HIGH-to-LOW transition, the data that
meets the setup times is latched. Data appears on the bus
when the Output Enable (OE
) is LOW. When OE is HIGH,
the bus output is in the high impedance state. In addition to
the LE and OE
pins, the ACT843 has a Clear (CLR) pin
and a Preset (PRE
) pin. These pins are ideal for parity bus
interfacing in high performance systems. When CLR
is
LOW, the outputs are LOW if OE
is LOW. When CLR is
HIGH, data can be entered into the latch. When PRE
is
LOW, the outputs are HIGH if OE
is LOW. Preset overrides
CLR
.
Function Tables
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
Logic Diagram
Inputs Internal Outputs
Function
CLR
PRE OE LE D Q O
HHHHL L Z High Z
HHHHH H Z High Z
H H H L X NC Z Latched
H H L H L L L Transparent
H H L H H H H Transparent
H H L L X NC NC Latched
H L L X X H H Preset
L H L X X L L Clear
LLLXX H H Preset
L H H L X L Z Clear/High Z
H L H L X H Z Preset/High Z
3 www.fairchildsemi.com
74ACT843
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Supply Voltage (V
CC
) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= −0.5V −20 mA
V
I
= V
CC
+0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to V
CC
+0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V −20 mA
V
O
= V
CC
+0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to V
CC
+0.5V
DC Output Source
or Sink Current (I
O
) ±50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) ±50 mA
Storage Temperature (T
STG
) −65°C to +150°C
Junction Temperature (T
J
)
PDIP 140
°C
Supply Voltage (V
CC
) 4.5V to 5.5V
Input Voltage (V
I
)0V to V
CC
Output Voltage (V
O
)0V to V
CC
Operating Temperature (T
A
) −40°C to +85°C
Minimum Input Edge Rate (
∆V/∆t) 125 mV/ns
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Symbol Parameter
V
CC
T
A
= +25°CT
A
= −40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 4.5 1.5 2.0 2.0
V
V
OUT
= 0.1V
Input Voltage 5.5 1.5 2.0 2.0 or V
CC
− 0.1V
V
IL
Maximum LOW Level 4.5 1.5 0.8 0.8
V
V
OUT
= 0.1V
Input Voltage 5.5 1.5 0.8 0.8 or V
CC
− 0.1V
V
OH
Minimum HIGH Level 4.5 4.49 4.4 4.4
VI
OUT
= −50 µA
Output Voltage 5.5 5.49 5.4 5.4
V
IN
= V
IL
or V
IH
4.5 3.86 3.76 V I
OH
= −24 mA
5.5 4.86 4.76 I
OH
= −24 mA (Note 2)
V
OL
Maximum LOW Level 4.5 0.001 0.1 0.1
VI
OUT
= 50 µA
Output Voltage 5.5 0.001 0.1 0.1
V
IN
= V
IL
or V
IH
4.5 0.36 0.44 V I
O
= 24 mA
5.5 0.36 0.44 I
OL
= 24 mA (Note 2)
I
IN
Maximum Input
5.5 ±0.1 ±1.0 µAV
I
= V
CC
, GND
Leakage Current
I
OZ
Maximum 3-STATE
5.5 ±0.5 ±5.0 µA
V
I
= V
IL
, V
IH
Leakage Current V
O
= V
CC
, GND
I
CCT
Maximum
5.5 0.6 1.5 mA V
I
= V
CC
− 2.1V
I
CC
/Input
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 3) 5.5 −75 mA V
OHD
= 3.85V Min
I
CC
Maximum Quiescent
5.5 8.0 80.0 µA
V
IN
= V
CC
Supply Current or GND
P1-P3P4-P6

74ACT843SCX

Mfr. #:
Buy 74ACT843SCX
Manufacturer:
ON Semiconductor
Description:
IC LATCH 9-BIT D-TYPE 24SOIC
Lifecycle:
New from this manufacturer.
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