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74VHC374MTCX
P1-P3
P4-P6
P7-P9
P10-P10
TC74VHC74F/FN/FT/FK
2007-10-01
4
Timing Requirements (input: t
r
= t
f
= 3 ns)
Test Condition
Ta =
25°C
Ta =
−
40 to
85°C
Characteristics Symbol
V
CC
(V)
Limit Limit
Unit
Minimum pulse width
(CK)
t
w (L)
t
w (H)
―
3.3 ± 0.3
5.0 ± 0.5
6.0
5.0
7.0
5.0
ns
Minimum pulse width
(
CLR ,
PR )
t
w (L)
―
3.3 ± 0.3
5.0 ± 0.5
6.0
5.0
7.0
5.0
ns
Minimum set-up time
t
s
―
3.3 ± 0.3
5.0 ± 0.5
6.0
5.0
7.0
5.0
ns
Minimum hold time
t
h
―
3.3 ± 0.3
5.0 ± 0.5
0.5
0.5
0.5
0.5
ns
Minimum removal time
(
CLR
,
PR
)
t
rem
―
3.3 ± 0.3
5.0 ± 0.5
5.0
3.0
5.0
3.0
ns
AC Characteristics
(input: t
r
= t
f
= 3 ns)
Test Condition
Ta = 25°C
Ta =
−
40 to 85°C
Characteristics Symbol
V
CC
(V)
C
L
(pF) Min
Typ.
Max Min Max
Unit
15
―
6.7 11.9 1.0 14.0
3.3 ± 0.3
50
―
9.2 15.4 1.0 17.5
15
―
4.6 7.3 1.0 8.5
Propagation delay
time
(CK-Q,
Q
)
t
pLH
t
pHL
―
5.0 ± 0.5
50
―
6.1 9.3 1.0
10.5
ns
15
―
7.6 12.3 1.0 14.5
3.3 ± 0.3
50
―
10.1
15.8 1.0 18.0
15
―
4.8 7.7 1.0 9.0
Propagation delay
time
(
CLR ,
PR -Q,
Q)
t
pLH
t
pHL
―
5.0 ± 0.5
50
―
6.3 9.7 1.0
11.0
ns
15 80
125
―
70
―
3.3 ± 0.3
50 50
75
―
45
―
15 130
170
―
110
―
Maximum clock
frequency
f
max
―
5.0 ± 0.5
50 90
115
―
75
―
MHz
Input capacitance
C
IN
―
―
4
10
―
10
pF
Power dissipation
capacitance
C
PD
(Note)
―
25
―
―
―
pF
Note: C
PD
is defined as the value of the internal equival
ent
capacitance which is ca
lculated from
the operating
current consumption without load.
Average operating current can be obta
ined by the equation:
I
CC (opr)
= C
PD
·V
CC
·f
IN
+ I
CC
/2 (per F/F)
TC74VHC74F/FN/FT/FK
2007-10-01
5
Input Equivalent Circuit
INPUT
TC74VHC74F/FN/FT/FK
2007-10-01
6
Package Dimensions
Weight: 0.18 g (typ.)
P1-P3
P4-P6
P7-P9
P10-P10
74VHC374MTCX
Mfr. #:
Buy 74VHC374MTCX
Manufacturer:
ON Semiconductor / Fairchild
Description:
Flip Flops Oct D-Type Flip-Flop
Lifecycle:
New from this manufacturer.
Delivery:
DHL
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Ups
TNT
EMS
Payment:
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