DS1705/DS1706
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the reset to an active state. When V
CC
returns to an in-tolerance condition, the reset signal is kept in the
active state for a minimum of 130 ms to allow the power supply and processor to stabilize.
The second function the DS1705/DS1706 performs is pushbutton reset control. The DS1705/DS1706
debounces the pushbutton input and guarantees an active reset pulse width of 130 ms minimum.
The third function is a watchdog timer. The DS1705/DS1706 has an internal timer that forces the WDS
output signal to the active state if the strobe input is not driven low prior to time-out.
OPERATION
Power Monitor
The DS1705/DS1706 detects out-of-tolerance power supply conditions and warns a processor-based
system of impending power failure. When V
CC
falls below the minimum V
CC
tolerance, a comparator
outputs the RST (or RST) signal. RST (or RST) is an excellent control signal for a microprocessor, as
processing is stopped at the last possible moment of valid V
CC
. On power-up, RST (or RST) are kept
active for a minimum of 130 ms to allow the power supply and processor to stabilize.
Pushbutton Reset
The DS1705/DS1706 provides an input pin for direct connection to a pushbutton reset (see Figure 2). The
pushbutton reset input requires an active low signal. Internally, this input is debounced and timed such
that a RST (or RST) signal of at least 130 ms minimum will be generated. The 130 ms delay commences
as the pushbutton reset input is released from the low level. The pushbutton can be initiated by connecting
the WDS or NMI outputs to the PBRST input as shown in Figure 3.
Non-Maskable Interrupt
The DS1705/DS1706 generates a non-maskable interrupt ( NMI ) for early warning of a power failure. A
precision comparator monitors the voltage level at the IN pin relative to an on-chip reference generated
by an internal band gap. The IN pin is a high impedance input allowing for a user-defined sense point. An
external resistor voltage divider network (Figure 5) is used to interface with high voltage signals. This
sense point may be derived from a regulated supply or from a higher DC voltage level closer to the main
system power input. Since the IN trip point V
TP
is 1.25 volts, the proper values for R1 and R2 can be
determined by the equation as shown in Figure 5. Proper operation of the DS1705/DS1706 requires that
the voltage at the IN pin be limited to V
CC
. Therefore, the maximum allowable voltage at the supply being
monitored (V
MAX
) can also be derived as shown in Figure 5. A simple approach to solving the equation is
to select a value for R2 high enough to keep power consumption low, and solve for R1. The flexibility of
the IN input pin allows for detection of power loss at the earliest point in a power supply system,
maximizing the amount of time for system shutdown between NMI and RST (or RST).
When the supply being monitored decays to the voltage sense point, the DS1705/DS1706 pulses the NMI
output to the active state for a minimum 200 ms. The
NMI power-fail detection circuitry also has built-in
hysteresis of 100 mV. The supply must be below the voltage sense point for approximately 5 ms before a
low
NMI will be generated. In this way, power supply noise is removed from the monitoring function,
preventing false interrupts. During a power-up, any detected IN pin levels below V
TP
by the comparator
are disabled from generating an interrupt until V
CC
rises to V
CCTP
. As a result, any potential NMI pulse
will not be initiated until V
CC
reaches V
CCTP
.
Connecting NMI to PBRST would allow non-maskable interrupt to generate an automatic reset when an
out-of-tolerance condition occurred in a monitored supply. An example is shown in Figure 3.
