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MT41J256M16LY-091G:N TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
Parameter Symbol
gDDR3-2000 gDDR3-2200
Unit NotesMin Max Min Max
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
t
IS
(AC150)
– – 170 – ps 29, 30
V
REF
@ 1 V/ns – – 320 – ps 20, 30
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
t
IS
(AC135)
65 – – – ps
V
REF
@ 1 V/ns 200 – – – ps
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
t
IS
(AC125)
150 – – – ps
V
REF
@ 1 V/ns 275 – – – ps
CTRL, CMD, ADDR hold
from CK,CK#
Base (specification)
t
IH
(DC100)
100 – 120 – ps 29, 30
V
REF
@ 1 V/ns 200 – 220 – ps 20, 30
Minimum CTRL, CMD, ADDR pulse width
t
IPW 620 – 560 – ps 41
ACTIVATE to internal READ or WRITE delay
t
RCD See corresponding speed bin table for
t
RCD
ns 31
PRECHARGE command period
t
RP See corresponding speed bin table for
t
RP
ns 31
ACTIVATE-to-PRECHARGE command period
t
RAS See corresponding speed bin table for
t
RAS
ns 31, 32
ACTIVATE-to-ACTIVATE command period
t
RC See corresponding speed bin table for
t
RC
ns 31
ACTIVATE-to-ACTIVATE
minimum command period
t
RRD MIN = greater of
4CK or 7.5ns
MIN = greater of
4CK or 6ns
CK 31
Four ACTIVATE
windows
t
FAW 35 – 35 – ns 31
Write recovery time
t
WR 15 N/A 15 N/A ns 31, 32,
33,34
Delay from start of internal WRITE transaction
to internal READ command
t
WTR MIN = greater of 4CK or 7.5ns; MAX =
N/A
CK 31, 34
READ-to-PRECHARGE time
t
RTP MIN = greater of 4CK or 7.5ns; MAX =
N/A
CK 31, 32
CAS#-to-CAS# command delay
t
CCD MIN = 4CK; MAX = N/A CK
Auto precharge write recovery + precharge
time
t
DAL MIN = WR +
t
RP/
t
CK (AVG); MAX = N/A CK
MODE REGISTER SET command cycle time
t
MRD MIN = 4CK; MAX = N/A CK
MODE REGISTER SET command update delay
t
MOD MIN = greater of 12CK or 15ns; MAX =
N/A
CK
MULTIPURPOSE REGISTER READ burst end to
mode register set for multipurpose register exit
t
MPRR MIN = 1CK; MAX = N/A CK
Calibration Timing
ZQCL command: Long
calibration time
POWER-UP and RE-
SET operation
t
ZQ
INIT
512 – 512 – CK
Normal operation
t
ZQ
OPER
256 – 256 – CK
4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions
CCMTD-1005363231-10344
ddr3_4gb_graphics_addendum 091.pdf - Rev. A 05/16 EN
13
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
Parameter Symbol
gDDR3-2000 gDDR3-2200
Unit NotesMin Max Min Max
ZQCS command: Short calibration time
t
ZQCS 64 – 64 – CK
Initialization and Reset Timing
Exit reset from CKE HIGH to a valid command
t
XPR MIN = greater of 5CK or
t
RFC + 10ns;
MAX = N/A
CK
Begin power supply ramp to power supplies
stable
t
VDDPR MIN = N/A; MAX = 200 ms
RESET# LOW to power supplies stable
t
RPS MIN = 0; MAX = 200 ms
RESET# LOW to I/O and R
TT
High-Z
t
IOZ MIN = N/A; MAX = 20 ns 35
Refresh Timing
REFRESH-to-ACTIVATE or REFRESH
command period
t
RFC MIN = 260; MAX = 70,200 ns
Maximum refresh
period
T
C
≤ 85°C – 64 (1X) ms 36
T
C
> 85°C 32 (2X) ms 36
Maximum average
periodic refresh
T
C
≤ 85°C
t
REFI 7.8 (64ms/8192) µs 36
T
C
> 85°C 3.9 (32ms/8192) µs 36
Self Refresh Timing
Exit self refresh to commands not requiring a
locked DLL
t
XS MIN = greater of 5CK or
t
RFC + 10ns;
MAX = N/A
CK
Exit self refresh to commands requiring a
locked DLL
t
XSDLL MIN =
t
DLLK (MIN); MAX = N/A CK 28
Minimum CKE low pulse width for self refresh
entry to self refresh exit timing
t
CKESR MIN =
t
CKE (MIN) + CK; MAX = N/A CK
Valid clocks after self refresh entry or power-
down entry
t
CKSRE MIN = greater of 5CK or 10ns; MAX =
N/A
CK
Valid clocks before self refresh exit,
power-down exit, or reset exit
t
CKSRX MIN = greater of 5CK or 10ns; MAX =
N/A
CK
Power-Down Timing
CKE MIN pulse width
t
CKE (MIN) Greater of 3CK or
5.625ns
Greater of 3CK or
5ns
CK
Command pass disable delay
t
CPDED MIN = 2;
MAX = N/A
MIN = 1;
MAX = N/A
CK
Power-down entry to power-down exit timing
t
PD MIN =
t
CKE (MIN); MAX = 9 ×
t
REFI CK
Begin power-down period prior to CKE regis-
tered HIGH
t
ANPD WL - 1CK CK
Power-down entry period: ODT either synchro-
nous or asynchronous
PDE Greater of
t
ANPD or
t
RFC - REFRESH
command to CKE LOW time
CK
Power-down exit period: ODT either
synchronous or asynchronous
PDX
t
ANPD +
t
XPDLL CK
Power-Down Entry Minimum Timing
4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions
CCMTD-1005363231-10344
ddr3_4gb_graphics_addendum 091.pdf - Rev. A 05/16 EN
14
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
Parameter Symbol
gDDR3-2000 gDDR3-2200
Unit NotesMin Max Min Max
ACTIVATE command to power-down entry
t
ACTPDEN MIN = 2 MIN = 1 CK
PRECHARGE/PRECHARGE ALL command to
power-down entry
t
PRPDEN MIN = 2 MIN = 1 CK
REFRESH command to power-down entry
t
REFPDEN MIN = 2 MIN = 1 CK 37
MRS command to power-down entry
t
MRSPDEN MIN =
t
MOD (MIN) CK
READ/READ with auto precharge command to
power-down entry
t
RDPDEN MIN = RL + 4 + 1 CK
WRITE command to
power-down entry
BL8 (OTF, MRS)
BC4OTF
t
WRPDEN MIN = WL + 4 +
t
WR/
t
CK (AVG) CK
BC4MRS
t
WRPDEN MIN = WL + 2 +
t
WR/
t
CK (AVG) CK
WRITE with auto pre-
charge command to
power-down entry
BL8 (OTF, MRS)
BC4OTF
t
WRAPDEN MIN = WL + 4 + WR + 1 CK
BC4MRS
t
WRAPDEN MIN = WL + 2 + WR + 1 CK
Power-Down Exit Timing
DLL on, any valid command, or DLL off to com-
mands not requiring locked DLL
t
XP MIN = greater of 3CK or 6ns; MAX =
N/A
CK
Precharge power-down with DLL off to com-
mands requiring a locked DLL
t
XPDLL MIN = greater of 10CK or 24ns; MAX =
N/A
CK 28
ODT Timing
R
TT
synchronous turn-on delay ODTL on CWL + AL - 2CK CK 38
R
TT
synchronous turn-off delay ODTL off CWL + AL - 2CK CK 40
R
TT
turn-on from ODTL on reference
t
AON –195 195 –195 195 ps 23, 38
R
TT
turn-off from ODTL off reference
t
AOF 0.3 0.7 0.3 0.7 CK 39, 40
Asynchronous R
TT
turn-on delay
(power-down with DLL off)
t
AONPD MIN = 2; MAX = 8.5 ns 38
Asynchronous R
TT
turn-off delay
(power-down with DLL off)
t
AOFPD MIN = 2; MAX = 8.5 ns 40
ODT HIGH time with WRITE command and BL8 ODTH8 MIN = 6; MAX = N/A CK
ODT HIGH time without WRITE command or
with WRITE command and BC4
ODTH4 MIN = 4; MAX = N/A CK
Dynamic ODT Timing
R
TT,nom
-to-R
TT(WR)
change skew ODTLcnw WL - 2CK CK
R
TT(WR)
-to-R
TT,nom
change skew - BC4 ODTLcnw4 4CK + ODTLoff CK
R
TT(WR)
-to-R
TT,nom
change skew - BL8 ODTLcnw8 6CK + ODTLoff CK
R
TT
dynamic change skew
t
ADC 0.3 0.7 0.3 0.7 CK 39
Write Leveling Timing
First DQS, DQS# rising edge
t
WLMRD 40 – 40 – CK
DQS, DQS# delay
t
WLDQSEN 25 – 25 – CK
4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions
CCMTD-1005363231-10344
ddr3_4gb_graphics_addendum 091.pdf - Rev. A 05/16 EN
15
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

MT41J256M16LY-091G:N TR

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Buy MT41J256M16LY-091G:N TR
Manufacturer:
Micron
Description:
IC DRAM 4G PARALLEL 1GHZ 96FBGA
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