NLV74HC573ADTR2G

© Semiconductor Components Industries, LLC, 2014
May, 2018 − Rev. 17
1 Publication Order Number:
MC74HC573A/D
MC74HC573A
Octal 3-State Noninverting
Transparent Latch
High−Performance Silicon−Gate CMOS
The MC74HC573A is identical in pinout to the LS573. The devices
are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
The HC573A is identical in function to the HC373A but has the data
inputs on the opposite side of the package from the outputs to facilitate
PC board layout.
Features
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
In Compliance with the JEDEC Standard No. 7.0 A Requirements
Chip Complexity: 218 FETs or 54.5 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
DATA
INPUTS
D0
D1
D2
D3
D4
D5
D6
D7
LATCH ENABLE
OUTPUT ENABLE
11
1
9
8
7
6
5
4
3
219
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PIN 20 = V
CC
PIN 10 = GND
NONINVERTING
OUTPUTS
LOGIC DIAGRAM
Design Criteria
*Equivalent to a two−input NAND gate.
Value Units
Internal Gate Count*
54.5 ea.
Internal Gate Progation Delay
1.5 ns
Internal Gate Power Dissipation
5.0 mW
Speed Power Product
0.0075 pJ
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1
20
MARKING DIAGRAMS
SOIC−20
DW SUFFIX
CASE 751D
74HC573A
AWLYYWWG
HC
573A
ALYWG
G
TSSOP−20
DT SUFFIX
CASE 948E
20
1
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
SOIC−20 TSSOP−20
D4
D2
D1
D0
OUTPUT
ENABLE
GND
D7
D6
D5
D3 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q3
Q2
Q1
Q0
V
CC
LATCH
ENABLE
Q7
Q6
Q5
Q4
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Output
Output Latch
Enable Enable D Q
LHHH
LHLL
L L X No Change
HXXZ
X = Don’t Care
Z = High Impedance
MC74HC573A
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2
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
V
in
DC Input Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Current, per Pin ±35 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±75 mA
P
D
Power Dissipation in Still Air, SOIC Package†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature –65 to +150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(TSSOP or SOIC Package)
260
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/°C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types –55 +125
_C
t
r
, t
f
Input Rise and Fall Time V
CC
= 2.0 V
(Figure 1) V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
1000
500
400
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbo
l
Parameter Test Conditions
V
CC
V
Guaranteed Limit
Unit
–55 to
25_C
v85_C v125_C
V
IH
Minimum High−Level Input Voltage V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| v 20 mA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
V
IL
Maximum Low−Level Input Voltage V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| v 20 mA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1 8
0.5
0.9
1.35
1.8
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
in
= V
IH
or V
IL
|I
out
| 2.4mA
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
V
OL
Maximum Low−Level Output
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| v 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
|I
out
| 2.4mA
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
I
in
Maximum Input Leakage Current V
in
= V
CC
or GND 6.0 ±0.1 ±1.0 ±1.0
mA
I
OZ
Maximum Three−State Leakage
Current
Output in High−Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
6.0 ±0.5 ±5.0 ±10
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
II
out
I = 0 mA
6.0 4.0 40 160
mA
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74HC573A
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3
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Symbo
l
Parameter
V
CC
V
Guaranteed Limit
Unit
–55 to 25_C v85_C v125_C
t
PLH
,
t
PHL
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
2.0
3.0
4.5
6.0
150
100
30
26
190
140
38
33
225
180
45
38
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
2.0
3.0
4.5
6.0
160
105
32
27
200
145
40
34
240
190
48
41
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
3.0
4.5
6.0
60
27
12
10
75
32
15
13
90
36
18
15
ns
C
in
Maximum Input Capacitance 10 10 10 pF
C
out
Maximum 3−State Output Capacitance (Output in High−Impedance State) 15 15 15 pF
C
PD
Power Dissipation Capacitance (Per Enabled Output)*
Typical @ 25°C, V
CC
= 5.0 V
pF
23
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
.
TIMING REQUIREMENTS (C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Symbo
l
Parameter Figure
V
CC
V
Guaranteed Limit
Unit
–55 to 25_C v85_C v125_C
Min Max Min Max Min Max
t
su
Minimum Setup Time, Input D to Latch Enable 4 2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
t
h
Minimum Hold Time, Latch Enable to Input D 4 2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
t
w
Minimum Pulse Width, Latch Enable 2 2.0
3.0
4.5
6.0
75
60
15
13
95
80
19
16
110
90
22
19
ns
t
r
, t
f
Maximum Input Rise and Fall Times 1 2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns

NLV74HC573ADTR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Counter Shift Registers LOG CMOS TRANS LATCH OCTL
Lifecycle:
New from this manufacturer.
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