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MAX4811CTN+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
MAX4810/MAX4811/MAX4812
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(V
DD
= +3.3V, V
CC
_ = +12V, V
EE
_ = -12V, V
SS
= -100V, V
PP
_ = +100V, V
NN
_ = -100V, f
OUT
= 5MHz, T
A
= +25°C, unless otherwise noted.)
0
20
18
16
14
12
10
8
6
4
2
22
132 45678910
I
NN
vs. OUTPUT FREQUENCY
MAX4810/11/12 toc10
FREQUENCY (MHz)
I
NN
(mA)
CONTINUOUS SWITCHING,
V
PP_
= V
CC_
= +5V,
V
NN_
= V
EE_
= -5V,
V
DD
= +3.3V, NO LOAD
0.40
0.52
0.48
0.44
0.60
0.56
0.76
0.72
0.68
0.64
0.80
0 10203040506070
I
NN
vs. TEMPERATURE
MAX4810/11/12 toc11
TEMPERATURE (
°
C)
I
NN
(mA)
4 PULSES AT 10MHz, PRF = 10kHz
0
3
2
1
5
4
9
8
7
6
10
0 10203040506070
I
NN
vs. TEMPERATURE
MAX4810/11/12 toc12
TEMPERATURE (
°
C)
I
NN
(mA)
CONTINUOUS SWITCHING,
f
OUT
= 2.5MHz,
V
PP_
= V
CC_
= +5V,
V
NN_
= V
EE_
= -5V,
V
DD
= +3.3V, NO LOAD
0
20
18
16
14
12
10
8
6
4
2
22
OUT RISE TIME (GND TO V
PP_
)
vs. V
CC_
/V
EE_
SUPPLY VOLTAGE
MAX4810/11/12 toc13
t
ROP
(ns)
V
CC_
/V
EE_
SUPPLY VOLTAGE (V)
+4.75/-4.75 +7.5/-7.5 +12/-12
+5/-5 +10/-10 +12.6/-12.6
R
L
= 100Ω, C
L
= 100pF
0
20
18
16
14
12
10
8
6
4
2
22
OUT FALL TIME (GND TO V
NN_
)
vs. V
CC_
/V
EE_
SUPPLY VOLTAGE
MAX4810/11/12 toc14
t
FON
(ns)
V
CC_
/V
EE_
SUPPLY VOLTAGE (V)
+4.75/-4.75 +7.5/-7.5 +12/-12
+5/-5 +10/-10 +12.6/-12.6
R
L
= 100Ω, C
L
= 100pF
10
12
11
13
14
15
16
17
18
19
20
21
22
INP-TO-OUT RISE PROPAGATION DELAY
vs. V
CC_
/V
EE_
SUPPLY VOLTAGE
MAX4810/11/12 toc15
V
CC_
/V
EE_
SUPPLY VOLTAGE (V)
t
PLH
(ns)
+4.75/-4.75 +7.5/-7.5 +12/-12
+5/-5 +10/-10 +12.6/-12.6
R
L
= 100Ω, C
L
= 100pF
0
6
4
2
10
8
18
16
14
12
20
0 10203040506070
INP-TO-OUT RISE PROPAGATION DELAY
vs. TEMPERATURE
MAX4810/11/12 toc16
TEMPERATURE (°C)
t
PLH
(ns)
R
L
= 100
Ω
, C
L
= 100pF
10
12
11
13
14
15
16
17
18
19
20
21
22
INP-TO-OUT FALL PROPAGATION DELAY
vs. V
CC_
/V
EE_
SUPPLY VOLTAGE
MAX4810/11/12 toc17
V
CC_
/V
EE_
SUPPLY VOLTAGE (V)
t
PHL
(ns)
+4.75/-4.75 +7.5/-7.5 +12/-12
+5/-5 +10/-10 +12.6/-12.6
R
L
= 100Ω, C
L
= 100pF
0
6
4
2
10
8
18
16
14
12
20
0 10203040506070
INP-TO-OUT FALL PROPAGATION DELAY
vs. TEMPERATURE
MAX4810/11/12 toc18
TEMPERATURE (°C)
t
PHL
(ns)
R
L
= 100
Ω
, C
L
= 100pF
MAX4810/MAX4811/MAX4812
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
8 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1
C
GP1
Channel 1 High-Side Gate Input. Connect a 1nF to 10nF capacitor between C
DP1
and C
GP1
as close as
possible to the device.
2 , 3
V
PP1
Channel 1 High-Side Positive Supply Voltage Input. Bypass V
PP1
to GND with a 0.1µF as close as
possible to the device. See the
Power Supplies and Bypassing
section. Depending on the output,
additional bypassing may be required.
4, 10, 33,
39
N.C. No Connection. Not connected internally.
5 OP1 Channel 1 High-Side Drain Output
6 OCP1 Channel 1 High-Side Clamp Output
7, 15, 28,
36, 44, 55
GND Ground
8 OCN1 Channel 1 Low-Side Clamp Output
9 ON1 Channel 1 Low-Side Drain Output
11, 12
V
NN1
Channel 1 High-Side Negative Supply Voltage Input. Bypass V
NN1
to GND with a 0.1µF as close as
possible to the device. See the
Power Supplies and Bypassing
section. Depending on the output,
additional bypassing may be required.
13
C
GN1
Channel 1 Low-Side Gate Input. Connect a 1nF to 10nF capacitor between C
DN1
and C
GN1
as close as
possible to the device.
14
C
DN1
Channel 1 Low-Side Driver Output. Connect a 1nF to 10nF capacitor between C
DN1
and C
GN1
as close
as possible to the device.
16, 54
V
CC1
Channel 1 Gate-Drive Supply Voltage Input. Bypass V
CC1
to GND with a 0.1µF as close as possible to
the device. See the
Power Supplies and Bypassing
section. Depending on the output, additional
bypassing may be required.
17 INN1 Channel 1 Low-Side Logic Input (Table 1)
18 INC1
Channel 1 Clamp Logic Input. Clamps OCP1 and OCN1 are turned on when INC1 is high and when INP1
and INN1 are low (see Table 1).
19 INP1 Channel 1 High-Side Logic Input (Table 1)
20 EN1
Channel 1 Enable Logic Input. Drive EN1 high to enable OP1 and ON1. Pull EN1 low to turn on the gate-
source short circuit (see Table 1).
21
SHDN
Shutdown Logic Input (Table 1)
22 AGND Analog Ground. Must be connected to common GND.
23 EN2
Channel 2 Enable Logic Input. Drive EN2 high to enable OP2 and ON2. Pull EN2 low to turn on the gate-
source short circuit. See Table 1.
24 INP2 Channel 2 High-Side Logic Input (Table 1)
25 INC2
Channel 2 Clamp Logic Input. Clamps OCP2 and OCN2 are turned on when INC2 is high and when INP2
and INN2 are low. See Table 1.
26 INN2 Channel 2 Low-Side Logic Input (Table 1)
27, 45
V
CC2
Channel 2 Gate-Drive Supply Voltage Input. Bypass V
CC2
to GND with a 0.1µF as close as possible to
the device. See the
Power Supplies and Bypassing
section. Depending on the output, additional
bypassing may be required.
29
C
DN2
Channel 2 Low-Side Driver Output. Connect a 1nF to 10nF capacitor between C
DN2
and C
GN2
as close
as possible to the device.
30
C
GN2
Channel 2 Low-Side Gate Input. Connect a 1nF to 10nF capacitor between C
DN2
and C
GN2
as close as
possible to the device.
MAX4810/MAX4811/MAX4812
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
_______________________________________________________________________________________ 9
Detailed Description
The MAX4810/MAX4811/MAX4812 are dual high-volt-
age, high-speed pulsers that can be independently
configured for either unipolar or bipolar pulse outputs.
These devices have independent logic inputs for full
pulse control and independent active clamps. The
clamp input, INC_, can be set high to activate the
clamp automatically when the device is not pulsing to
the positive or negative high-voltage supplies.
Logic Inputs (INP_, INN_, INC_, EN_,
SHDN
)
The MAX4810/MAX4811/MAX4812 have a total of nine
logic input signals. SHDN controls power-up and power-
down of the device. There are two sets of INP_, INN_,
INC_, and EN_ signals: one for each channel. INP_
PIN NAME FUNCTION
31, 32
V
NN2
Channel 2 High-Side Negative Supply Voltage Input. Bypass V
NN2
to GND with a 0.1µF as close as
possible to the device. See the
Power Supplies and Bypassing
section. Depending on the output,
additional bypassing may be required.
34 ON2 Channel 2 Low-Side Drain Output
35 OCN2 Channel 2 Low-Side Clamp Output
37 OCP2 Channel 2 High-Side Clamp Output
38 OP2 Channel 2 High-Side Drain Output
40, 41
V
PP2
Channel 2 High-Side Supply Voltage Input. Bypass V
PP2
to GND with a 0.1µF as close as possible to the
device. See the
Power Supplies and Bypassing
section. Depending on the output, additional bypassing
may be required.
42
C
GP2
Channel 2 High-Side Gate Input. Connect a 1nF to 10nF capacitor between C
DP2
and C
GP2
as close as
possible to the device.
43
C
DP2
Channel 2 High-Side Driver Output. Connect a 1nF to 10nF capacitor between C
DP2
and C
GP2
as close
as possible to the device.
46
C
GC2
Channel 2 High-Side Clamp Gate Input. Connect a 1nF to 10nF capacitor between C
DC2
and C
GC2
as
close as possible to the device.
47
C
DC2
Channel 2 High-Side Clamp Driver Output. Connect a 1nF to 10nF capacitor between C
DC2
and C
GC2
as
close as possible to the device.
48
V
EE2
Channel 2 Negative Supply Input. |V
EE2
|
≤
V
CC2
. Gate Drive Supply Voltage for the OCP clamp. Bypass
V
EE2
to GND with a 0.1µF as close as possible to the device. See the
Power Supplies and Bypassing
section. Depending on the output, additional bypassing may be required.
49
V
DD
Logic Supply Voltage Input. Bypass V
DD
to GND with a 0.1µF as close as possible to the device. See the
Power Supplies and Bypassing
section. Depending on the output, additional bypassing may be
required.
50
V
SS
Substrate Voltage. Connect V
SS
to a voltage equal to or more negative than the more negative of V
NN1
or
V
NN2
.
51
V
EE1
Channel 1 Negative Supply Input. |V
EE1
|
≤
V
CC1
. Gate Drive Supply Voltage for the OCP clamp. Bypass
V
EE1
to GND with a 0.1µF as close as possible to the device. See the
Power Supplies and Bypassing
section. Depending on the output, additional bypassing may be required.
52
C
DC1
Channel 1 High-Side Clamp Driver Output. Connect a 1nF to 10nF capacitor between C
DC1
and C
GC1
as
close as possible to the device.
53
C
GC1
Channel 1 High-Side Clamp Gate Input. Connect a 1nF to 10nF capacitor between C
DC1
and C
GC1
as
close as possible to the device.
56
C
DP1
Channel 1 High-Side Driver Output. Connect a 1nF to 10nF capacitor between C
DP1
and C
GP1
as close
as possible to the device.
—EP
Exposed Pad. EP must be connected to V
SS
. Do not use EP as the only V
SS
connection for the device.
Pin Description (continued)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

MAX4811CTN+

Mfr. #:
Buy MAX4811CTN+
Manufacturer:
Maxim Integrated
Description:
Timers & Support Products Dual Uni/Bi-polar Digital Pulser
Lifecycle:
New from this manufacturer.
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