FSA1156L6X Datasheet FSA1156L6X, MAX4529CUT-T, MAX4529CSA | P7-P9

MAX4529

Low-Voltage, Bidirectional

RF/Video Switch

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Pin Description

FUNCTION*

SOT23-6

NAME

Analog Switch Common** Terminal. Analog signal voltages should never exceed

V+ or V-.

—

Not Internally Connected

COM

Analog Switch Normally Closed** Terminal

Positive Supply-Voltage Input (analog and digital). The voltage difference between

V+ and V- should never exceed 12V.

5 RF and Logic Ground. Connect to ground plane.

3 -5V Supply Input. Connect to GND for single-supply operation.

DIP/SO/µMAX

1, 6

N.C.

V+

GND

V-

* All pins except N.C. have ESD diodes to V- and V+.

** NC and COM pins are identical and interchangeable. Either may be considered as an input or output; signals pass equally well in

either direction.

Theory of Operation

Logic-Level Translators

The MAX4529 is constructed as a high-frequency “T”

switch, as shown in Figure 1. The logic-level input, IN,

is translated by amplifier A1 into a V+ to V- logic signal

that drives inverter A2. Amplifier A2 drives the gates of

N-channel MOSFETs N1 and N2 from V+ to V-, turning

them fully on or off. The same signal drives inverter A3

(which drives the P-channel MOSFETs P1 and P2) from

V+ to V-, turning them fully on or off, and drives the N-

channel MOSFET N3 off and on.

The logic-level threshold is determined by V+ and

GND. The voltage on GND is usually at ground poten-

tial, but it may be set to any voltage between

(V+ - 2V) and V-. When the voltage between V+ and

GND is less than 2V, the level translators become very

slow and unreliable. Normally, GND should be connect-

ed to the ground plane.

Switch On Condition

When the switch is on, MOSFETs N1, N2, P1, and P2

are on and MOSFET N3 is off. The signal path is COM to

NC, and because both N-channel and P-channel

MOSFETs act as pure resistances, it is symmetrical (i.e.,

signals may pass in either direction). The off MOSFET,

N3, has no DC conduction, but has a small amount of

capacitance to GND. The four on MOSFETs also have

capacitance to ground that, together with the series

resistance, forms a lowpass filter. All of these capaci-

tances are distributed evenly along the series resis-

tance, so they act as a transmission line rather than a

simple R-C filter. This helps to explain the exceptional

300MHz bandwidth when the switches are on.

Typical attenuation in 50Ω systems is -2dB and is rea-

sonably flat up to 100MHz. Higher-impedance circuits

show even lower attenuation (and vice versa), but

slightly lower bandwidth due to the increased effect of

the internal and external capacitance and the switch’s

internal resistance.

A1 A2 A3

V-

GND

V+

V-

COM NC

NORMALLY CLOSED SWITCH CONSTRUCTION

COM - NCIN

OFF

ESD DIODES

ON GND, IN,

COM, AND NC

Figure 1. T-Switch Construction

4 Logic-Level Control Input. Logic-level voltages should never exceed V+ or V-.4 IN

The MAX4529 is a optimized for ±5V operation. Using

lower supply voltages or a single supply increases

switching time, on-resistance (and therefore on-state

attenuation), and nonlinearity.

Switch Off Condition

When the switch is off, MOSFETs N1, N2, P1, and P2

are off and MOSFET N3 is on. The signal path is

through the off-capacitances of the series MOSFETs,

but it is shunted to ground by N3. This forms a high-

pass filter whose exact characteristics depend on the

source and load impedances. In 50Ω systems, and

below 10MHz, the attenuation can exceed 80dB. This

value decreases with increasing frequency and

increasing circuit impedances. External capacitance

and board layout have a major role in determining over-

all performance.

Applications Information

Power-Supply Considerations

Overview

The MAX4529’s construction is typical of most CMOS

analog switches. It has three supply pins: V+, V-, and

GND. V+ and V- are used to drive the internal CMOS

switches and set the limits of the analog voltage on any

switch. Reverse ESD protection diodes are internally

connected between each analog signal pin and both

V+ and V-. If the voltage on any pin exceeds V+ or V-,

one of these diodes will conduct. During normal opera-

tion these reverse-biased ESD diodes leak, forming the

only current drawn from V-.

Virtually all the analog leakage current is through the

ESD diodes. Although the ESD diodes on a given sig-

nal pin are identical, and therefore fairly well balanced,

they are reverse biased differently. Each is biased by

either V+ or V- and the analog signal. This means their

leakages vary as the signal varies. The difference in the

two diode leakages from the signal path to the V+ and

V- pins constitutes the analog signal-path leakage cur-

rent. All analog leakage current flows to the supply ter-

minals, not to the other switch terminal. This explains

how both sides of a given switch can show leakage

currents of either the same or opposite polarity.

When the switch is on, there is no connection between

the analog signal paths and GND. The analog signal

paths consist of an N-channel and P-channel MOSFET

with their sources and drains paralleled and their gates

driven out of phase with V+ and V- by the logic-level

translators.

V+ and GND power the internal logic and logic-level

translators, and set the input logic thresholds. The

logic-level translators convert the logic levels to

switched V+ and V- signals to drive the gates of the

analog switches. This drive signal is the only connec-

tion between the logic supplies and the analog sup-

plies. All pins have ESD protection to V+ and to V-.

Increasing V- has no effect on the logic-level thresh-

olds, but it does increase the drive to the P-channel

switches, reducing their on-resistance. V- also sets the

negative limit of the analog signal voltage.

The logic-level thresholds are CMOS and TTL compati-

ble when V+ is +5V. As V+ is raised, the threshold

increases slightly; when V+ reaches +12V, the level

threshold is about 3.1V, which is above the TTL output

high-level minimum of 2.8V, but still compatible with

CMOS outputs.

Bipolar-Supply Operation

The MAX4529 operates with bipolar supplies between

±2.7V and ±6V. The V+ and V- supplies need not be

symmetrical, but their sum cannot exceed the absolute

maximum rating of 13.0V. Do not connect the

MAX4529 V+ pin to +3V and connect the logic-level

input pins to TTL logic-level signals. TTL logic-level

outputs can exceed the absolute maximum ratings,

causing damage to the part and/or external circuits.

CAUTION:

The absolute maximum V+ to V- differential

voltage is 13.0V. Typical “±6-Volt” or “12-Volt”

supplies with ±10% tolerances can be as high

as 13.2V. This voltage can damage the

MAX4529. Even ±5% tolerance supplies may

have overshoot or noise spikes that exceed

13.0V.

Single-Supply Operation

The MAX4529 operates from a single supply between

+2.7V and +12V when V- is connected to GND. All of

the bipolar precautions must be observed. Note, how-

ever, that these parts are optimized for ±5V operation,

and most AC and DC characteristics are degraded sig-

nificantly when departing from ±5V. As the overall sup-

ply voltage (V+ to V-) is lowered, switching speed,

on-resistance, off isolation, and distortion are degraded

(see Typical Operating Characteristics).

Single-supply operation also limits signal levels and

interferes with grounded signals. When V- = 0V, AC sig-

nals are limited to -0.3V. Voltages below -0.3V can be

clipped by the internal ESD-protection diodes, and the

parts can be damaged if excessive current flows.

MAX4529

Low-Voltage, Bidirectional

RF/Video Switch

8 _______________________________________________________________________________________

MAX4529

Low-Voltage, Bidirectional

RF/Video Switch

_______________________________________________________________________________________ 9

Single-Supply Operation Above 5V

The MAX4529 is designed for operation from single

+5V or dual ±5V supplies. As V+ is increased above

5V, the logic-level threshold voltage increases and the

supply current increases. In addition, if the logic levels

are not driven rail-to-rail, the analog signal pins, COM

and NC, can conduct a significant DC current (up to

1mA) to the supply pins. This current can add an

unwanted DC bias to the signal. Therefore, when oper-

ating V+ above 5V, always drive the IN pin rail-to-rail.

Power Off

When power to the MAX4529 is off (i.e., V+ = 0V and V-

= 0V), the Absolute Maximum Ratings still apply. This

means that neither logic-level inputs on IN nor signals

on COM or NC can exceed ±0.3V. Voltages beyond

±0.3V cause the internal ESD-protection diodes to con-

duct, and the parts can be damaged if excessive cur-

rent flows.

Grounding

DC Ground Considerations

Satisfactory high-frequency operation requires that

careful consideration be given to grounding. For most

applications, a ground plane is strongly recom-

mended, and GND should be connected to it with

solid copper.

In systems that have separate digital and analog (sig-

nal) grounds, connect these switch GND pins to analog

ground. Preserving a good signal ground is much more

important than preserving a digital ground. Ground cur-

rent is only a few nanoamps.

The logic-level input, IN, has voltage thresholds deter-

mined by V+ and GND. (V- does not influence the

logic-level threshold.) With +5V and 0V applied to V+

and GND, the threshold is about 1.6V, ensuring com-

patibility with TTL- and CMOS-logic drivers.

The GND pin can be connected to separate voltage

potentials if the logic-level input is not a normal logic

signal. (The GND voltage cannot exceed (V+ - 2V) or V-.)

Elevating GND reduces off isolation. Note, however,

that IN can be driven more negative than GND, as far

as V-. GND does not have to be removed from 0V when

IN is driven from bipolar sources, but the voltage on IN

should never exceed V-. GND should be separated

from 0V only if the logic-level threshold has to be

changed.

If the GND pin is not connected to 0V, it should be

bypassed to the ground plane with a surface-mount

10nF capacitor to maintain good RF grounding. DC

current in the IN and GND pins is less than 1nA, but

increases with switching frequency.

AC Ground and Bypassing

A ground plane is mandatory for satisfactory high-

frequency operation. (Prototyping using hand wiring

or wire-wrap boards is strongly discouraged.) Connect

any 0V GND pins to the ground plane with solid cop-

per. (The GND pin extends the high-frequency ground

through the package wire-frame, into the silicon itself,

thus improving isolation.) The ground plane should be

solid metal underneath the device, without interrup-

tions. There should be no traces under the device itself.

For DIP packages, this applies to both sides of a two-

sided board. Failure to observe this will have a minimal

effect on the “on” characteristics of the switch at high

frequencies, but it will degrade the off isolation and

crosstalk.

V+ and V- pins should be bypassed to the ground

plane with surface-mount 10nF capacitors. For DIP

packages, they should be mounted as close as possi-

ble to the pins on the same side of the board as the

device. Do not use feedthroughs or vias for bypass

capacitors. For surface-mount packages, the pins are

so close to each other that the bypass capacitors

should be mounted on the opposite side of the board

from the device. In this case, use short feedthroughs or

vias, directly under the V+ and V- pins. Any GND pin

not connected to 0V should be similarly bypassed. If V-

is 0V, connect it directly to the ground plane with solid

copper. Keep all leads short.

Signal Routing

Keep all signal leads as short as possible. Separate all

signal leads from each other and other traces with the

ground plane on both sides of the board. Where possi-

ble, use coaxial cable instead of printed circuit board

traces.

Board Layout

IC sockets degrade high-frequency performance and

should not be used if signal bandwidth exceeds 5MHz.

Surface-mount parts, having shorter internal lead

frames, provide the best high-frequency performance.

Keep all bypass capacitors close to the device, and

separate all signal leads with ground planes. Such

grounds tend to be wedge-shaped as they get closer to

the device. Use vias to connect the ground planes on

each side of the board, and place the vias in the apex of

the wedge-shaped grounds that separate signal leads.

Logic-level signal lead placement is not critical.

P1-P3 P4-P6 P7-P9 P10-P12

FSA1156L6X

Mfr. #:

Buy FSA1156L6X

Manufacturer:

ON Semiconductor / Fairchild

Description:

Analog Switch ICs Low RON Low Voltage SPST Analog Switch

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FSA1156L6X

FSA1156L6X

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