AD8314
Rev. B | Page 15 of 20
Figure 37 shows a third method for coupling the input signal
into the AD8314, applicable in applications where the input
signal is larger than the input range of the log amp. A series
resistor, connected to the RF source, combines with the input
impedance of the AD8314 to resistively divide the input signal
being applied to the input. This has the advantage of very little
power being tapped off in RF power transmission applications.
Table 5. X1 and X2 Recommended Components in Figure 36
Frequency (GHz) X1 X2 Voltage Gain (dB)
0.1 Short 52.3 Ω
0.9 33 nH 39 nH 11.8
1.9 10 nH 15 nH 7.8
2.5 1.5 pF 3.9 nH 2.55
INCREASING THE LOGARITHMIC SLOPE IN
MEASUREMENT MODE
The nominal logarithmic slope of 21.5 mV/dB (see Figure 10
for the variation of slope with frequency) can be increased to an
arbitrarily high value by attenuating the signal between V_UP
and VSET, as shown in
Figure 38. The ratio R1/R2 is set by
12/1
=
SlopeOriginal
SlopeNew
RR
In the example shown, two 5 kΩ resistors combine to change
the slope at 1900 MHz from 20 mV/dB to 40 mV/dB. The slope
can be increased to higher levels. This, however, reduces the
usable dynamic range of the device.
AD8314
R2
5k
R1
5k
V_UP
VSET
40mV/dB
@ 1900MHz
01086-038
Figure 38. Increasing the Output Slope
EFFECT OF WAVEFORM TYPE ON INTERCEPT
Although specified for input levels in dBm (dB relative to
1 mW), the AD8314 fundamentally responds to voltage and not
to power. A direct consequence of this characteristic is that
input signals of equal rms power but differing crest factors
produces different results at the log amps output.
The effect of differing signal waveforms is to shift the effective
value of the intercept upwards or downwards. Graphically, this
looks like a vertical shift in the log amps transfer function. The
logarithmic slope, however, is not affected. For example,
consider the case of the AD8314 being alternately fed by an
unmodulated sine wave and by a single CDMA channel of the
same rms power. The AD8314’s output voltage differs by the
equivalent of 3.55 dB (70 mV) over the complete dynamic range
of the device (the output for a CDMA input being lower).
Table 6 shows the correction factors that should be applied to
measure the rms signal strength of various signal types. A sine
wave input is used as a reference. To measure the rms power of
a square wave, for example, the mV equivalent of the dB value
given in the table (20 mV/dB times 3.01 dB) should be
subtracted from the output voltage of the AD8314.
Table 6. Shift in AD8314 Output for Signals with Differing
Crest Factors
Signal Type
Correction
Factor (Add
to Measured
Input Level)
Sine Wave 0 dB
Square Wave −3.01 dB
GSM Channel (All Time Slots On) +0.55 dB
CDMA Channel (Forward Link, 9 Channels On) +3.55 dB
CDMA Channel (Reverse Link) +0.5 dB
PDC Channel (All Time Slots On) +0.58 dB
AD8314
Rev. B | Page 16 of 20
MOBILE HANDSET POWER CONTROL EXAMPLES
Figure 39 shows a complete power amplifier control circuit for a
dual mode handset. This circuit is applicable to any dual mode
handset using TDMA or CDMA technologies. The PF08107B
(Hitachi) is driven by a nominal power level of 3 dBm. Some of
the output power from the PA is coupled off using an
LDC15D190A0007A (Murata) directional coupler. This has a
coupling factor of approximately 19 dB for its lower frequency
band (897.5 MHz ± 17.5 MHz) and 14 dB for its upper band
(1747.5 MHz ± 37.5 MHz) and an insertion loss of 0.38 dB
and 0.45 dB, respectively. Because the PF08107B transmits a
maximum power level of 35 dBm, additional attenuation of
15 dB is required before the coupled signal is applied to
the AD8314.
V
S
2.7V
VSET
0V TO 1.1V
PF08107B
(HITACHI)
PIN BAND 1
3dBm
PIN BAND 2
3dBm
1000pF
0dBm
MAX
ATTN
15dB
C
F
220pF
POUT BAND 2
32dBm MAX
POUT BAND 1
35dBm MAX
TO
ANTENNA
7
8
5
1
4
3
26
LDC15D190A0007A
BAND
SELECT
0V/2V
3.5V
V
CTL
V
APC
52.3
49.9
V
S
1
2
3
4
ENBL
RFIN
AD8314
8
7
6
5
VSET
FLTR
V_DN
VPOS
COMM
V_UP
0.1µF
4.7µF
0
1086-039
Figure 39. A Dual Mode Power Amplifier Control Circuit
The setpoint voltage, in the 0 V to 1.1 V range, is applied to the
VSET pin of the AD8314. This is typically supplied by a DAC.
This voltage is compared to the input level of the AD8314. Any
imbalance between VSET and the RF input level is corrected by
V_DN, which drives the V
APC
(gain control) of the power
amplifier. V_DN reaches a maximum value of approximately
1.9 V on a 2.7 V supply (this is higher for higher supply
voltages) while delivering approximately 3 mA to the V
APC
input.
A filter capacitor (C
F
) must be used to stabilize the loop. The
choice of C
F
depends to a large degree on the gain control
dynamics of the power amplifier, something that is frequently
characterized poorly, so some trial and error can be necessary.
In this example, a 220 pF capacitor gives the loop sufficient
speed to follow the GSM and DCS1800 time slot ramping
profiles, while still having a stable, critically damped response.
AD8314
Rev. B | Page 17 of 20
VSET (V)
POUT (dBm)
Figure 40 shows the relationship between the setpoint voltage,
V
SET
and output power at 0.9 GHz. The overall gain control
function is linear in dB for a dynamic range of over 40 dB.
Figure 41 shows a similar circuit for a single band handset
power amplifier. The BGY241 (Phillips) is driven by a nominal
power level of 0 dBm. A 20 dB directional coupler, DC09-73
(Alpha), is used to couple the signal in this case.
Figure 42
shows the relationship between the control voltage and the
output power at 0.9 GHz.
In both of these examples, noise on the V_DN pin can be reduced
by placing a simple RC low-pass filter between V
DN
and the gain
control pin of the power amplifier. However, the value of the
resistor should be kept low to minimize the voltage drop across
it due to the dc current flowing into the gain control input.
40
–30
01
.2
30
20
10
0
–10
–20
0.2 0.4 0.6 0.8 1.0
01086-040
Figure 40. POUT vs. VSET at 0.9 GHz for Dual Mode Handset Power Amplifier
Application
V
S
2.7V
VSET
0V TO 1.1
0dBm
MAX
ATTN
15dB
C
F
220pF
TO
ANTENNA
52.3
V
S
1
2
3
4
ENBL
RFIN
AD8314
8
7
6
5
VSET
FLTR
V_DN
VPOS
COMM
V_UP
0.1µF
RF INPUT
35dBm
MAX
47µF
BGY241
15dBm
2.2µF
680pF
P
IN
0dBm
DC09-73
6
3
4
5
12
3.5
V
01086-041
Figure 41. A Single Mode Power Amplifier Control Circuit
40
–50
0
VSET (V)
POUT (dBm)
30
20
10
0
–10
–20
–30
–40
0.2 0.4 0.6 0.8 1.0
01086-042
Figure 42. POUT vs. VSET at 0.9 GHz for Single Mode Handset

AD8314ACPZ-RL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
RF Detector RF Detector/Cntlr 100MHz-2.7GHz 45dB
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union