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CY24130ZXC-1

P1-P3P4-P6
CY24130
HOTLink II™ SMPTE Receiver Training
Clock
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-07711 Rev. *A Revised May 22, 2008
Features
■ Integrated phase-locked loop
■ Low-jitter, high-accuracy outputs
■ 3.3V operation
Benefits
■ Internal PLL with up to 400-MHz internal operation
■ Meets critical timing requirements in complex system
designs
■ Enables application compatibility
Table 1. Frequency table
Part Number Outputs Input Frequency Output Frequency Range
CY24130-1 2 27 MHz (Driven Reference) 1 copy 27-MHz reference clock output
1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable)
CY24130-2 2 27 MHz (Crystal Reference) 1 copy 27-MHz reference clock output
1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable)
XIN
XOUT
OUTPUT
MULTIPLEXER
AND
DIVIDERS
PLL
OSC.
CLKA
Q
P
VCO
VDDL
AVSS
Φ
AVDD
VSS
S0
S1
REFCLK
S2
VDD
VSSL
Logic Block Diagram
Table 2. Frequency Select Options
S2 S1 S0 CLKA REFCLK Units
0 0 0 27 27 MHz
0 0 1 36 27 MHz
0 1 0 54 27 MHz
0 1 1 148.50 27 MHz
100 74.25 27MHz
1 0 1 OFF, pulled low 27 MHz
1 1 0 OFF, pulled low 27 MHz
1 1 1 OFF, pulled low 27 MHz
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CY24130
Document #: 38-07711 Rev. *A Page 2 of 6
Pin Configuration
Figure 1. CY24130-1, -2, 16-pin TSSOP
Table 3. Pin Definition
Name Pin Number Description
XIN 1 Reference Crystal Input.
V
DD
2 Voltage Supply.
AV
DD
3 Analog Voltage Supply.
S0 4 Frequency Select 0.
AV
SS
5 Analog Ground.
V
SSL
6 VDDL Ground.
N/C 7 No Connect.
CLKA 8 27-/36-/54-/148.50-/74.25-MHz Clock Output (frequency selectable).
N/C 9 No Connect.
S1 10 Frequency Select 1.
V
DDL
11 Voltage Supply.
N/C 12 No Connect.
VSS 13 Ground.
REFCLK 14 Reference Clock Output.
S2 15 Frequency Select 2.
XOUT 16 Reference Crystal Output. Leave floating for -1.
Absolute Maximum Conditions
Parameter Description Min. Max. Unit
V
DD,
AV
DD
Supply Voltage –0.5 7.0 V
V
DDL
I/O Supply Voltage – 7.0 V
T
J
Junction Temperature – 125 °C
Digital Inputs AV
SS
– 0.3 AV
DD
+ 0.3 V
Electro-Static Discharge 2 – kV
Recommended Operating Conditions
Parameter Description Min. Typ. Max. Unit
V
DD
/AV
DDL
/V
DDL
Operating Voltage 3.135 3.3 3.465 V
T
A
Ambient Temperature 0 – 70 °C
C
LOAD
Max. Load Capacitance – – 15 pF
f
REF
Reference Frequency – 27 – MHz
C
LNOM
Nominal Parallel Crystal Load
Capacitance for -2
–18
–
pF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
VSSL
S1
XIN
XOUT
VDD
S0
AVSS
N/C
S2
REFCLK
AVDD
VDDL
N/C
N/C
CLKA
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CY24130
Document #: 38-07711 Rev. *A Page 3 of 6
Figure 2. Test and Measurement Setup
Voltage and Timing Definitions
Figure 3. Duty Cycle Definitions
Note
1. Not 100% tested.
DC Electrical Specifications
Parameter
[1]
Name Description Min. Typ. Max. Unit
I
OH
Output High Current V
OH
= V
DD
– 0.5, V
DD
/V
DDL
= 3.3V 12 24 – mA
I
OL
Output Low Current V
OL
= 0.5, V
DD
/V
DDL
= 3.3V 12 24 – mA
I
IH
Input High Current V
IH
= V
DD
–510μA
I
IL
Input Low Current V
IL
= 0V – – 10 μA
V
IH
Input High Voltage CMOS levels, 70% of V
DD
0.7 – – V
V
IL
Input Low Voltage CMOS levels, 30% of V
DD
––0.3V
I
VDD
Supply Current AV
DD
/V
DD
Current –16–mA
I
VDDL
Supply Current V
DDL
Current – 14 – mA
AC Electrical Specifications
Parameter
[1]
Name Description Min. Typ. Max. Unit
DC Output Duty Cycle Duty Cycle is defined in Figure 3; t
1
/t
2
, 50% of
V
DD
45 50 55 %
ER Rising Edge Rate Output Clock Edge Rate, Measured from 20% to
80% of V
DD
, C
LOAD
= 15 pF. See Figure 4.
0.8 1.4 – V/ns
EF Falling Edge Rate Output Clock Edge Rate, Measured from 80% to
20% of V
DD
, C
LOAD
= 15 pF. See Figure 4.
0.8 1.4 – V/ns
t
9
Clock Jitter CLKA Peak-Peak Period Jitter – 100 – ps
t
10
PLL Lock Time – – 3 ms
0.1
μ
F
V
DDs
Outputs
C
LOAD
GND
DUT
Clock
Output
V
DD
50% of V
DD
0V
t
1
t
2
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P1-P3P4-P6

CY24130ZXC-1

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Manufacturer:
Cypress Semiconductor
Description:
Clock Buffer MediaClock Clock
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