APEK4931MET-01-T-DK Datasheet A4931METTR-T, APEK4931MET-01-T-DK | P7-P9

3-Phase Brushless DC Motor Pre-Driver

A4931

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Current Regulation Load current is regulated by an internal

fixed off-time PWM control circuit. When the outputs of the full

bridge are turned on, current increases in the motor winding until

it reaches a value, I

TRIP

, given by:

TRIP

= 200 mV / R

SENSE .

When I

TRIP

is reached, the sense comparator resets the source

enable latch, turning off the source driver. At this point, load

inductance causes the current to recirculate for the fixed off-time

period.

Enable Logic The Enable input terminal (ENB pin) allows

external PWM. ENB low turns on the selected sink-source pair.

ENB high switches off the appropriate drivers and the load

current decays. If ENB is held low, the current will rise until it

reaches the level set by the internal current control circuit. Typi-

cally PWM frequency is in 20 kHz to 30 kHz range. If the ENB

high pulse width exceeds 3 ms, the gate outputs are disabled. The

Enable logic is summarized in the following table:

ENB Pin Setting Outputs Outputs State

0 On Drive

1 Source Chopped

Slow Decay with

Synchronous

Rectification

1 for > 3 ms typical Off Disable

Fixed Off-Time The A4931 fixed off-time is set to 25 μs

nominal.

PWM Blank Timer When a source driver turns on, a current

spike occurs due to the reverse recovery currents of the clamp

diodes as well as switching transients related to distributed

capacitance in the load. To prevent this current spike from errone-

ously resetting the source Enable latch, the sense comparator is

blanked. The blanking timer runs after the off-time counter com-

pletes, in order to provide the blanking function. The blanking

timer is reset when ENB is chopped or DIR is changed. With

external PWM control, a DIR change or an ENB on triggers the

blanking function. The duration is fixed at 1.5 μs.

Synchronous Rectification When a PWM-off cycle is

triggered, either by a chop command on ENB or by an internal

fixed off-time cycle, load current recirculates. The A4931 syn-

chronous rectification feature turns on the appropriate MOSFETs

during the current decay, and effectively shorts out the body

diodes with the low R

DS(on)

driver. This lowers power dissipation

significantly and can eliminate the need for external Schottky

diodes.

Brake Mode A logic low on the BRAKEZ pin activates Brake

mode. A logic high allows normal operation. Braking turns on all

three sink drivers, effectively shorting out the motor-generated

BEMF. The BRAKEZ input overrides the ENB input and also the

Lock Detect function.

It is important to note that the internal PWM current control cir-

cuit does not limit the current when braking, because the current

does not flow through the sense resistor. The maximum current

can be approximated by V

BEMF

/ R

LOAD

. Care should be taken to

insure that the maximum ratings of the A4391 are not exceeded

in the worse case braking situation, high speed and high inertial

load.

HBIAS Function This function provides a power supply of

7.5 V, current-limited to 30 mA. This reference voltage is used to

power the logic sections of the IC and also to power the external

Hall elements.

Standby Mode To prevent excessive power dissipation due

to the current draw of the external Hall elements, Standby mode

turns off the HBIAS output voltage. Standby mode is triggered

Functional Description

3-Phase Brushless DC Motor Pre-Driver

A4931

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

by holding ENB high for longer than 3 ms. Note that Brake mode

overrides Standby mode, so hold the BRAKEZ pin high in order

to enter Standby mode.

Charge Pump The internal charge pump is used to generate a

supply above V

to drive the high-side MOSFETs. The volt-

age on the VCP pin is internally monitored, and in case of a fault

condition, the outputs of the device are disabled.

Fault Shutdown In the event of a fault due to excessive

junction temperature or due to low voltage on VCP or VBB,

the outputs of the device are disabled until the fault condition is

removed. At power-up the UVLO circuit disables the drivers.

Overvoltage Protection VBB is monitored to determine if

a hazardous voltage is present due to the motor generator pump-

ing up the supply bus. When the voltage exceeds V

BBOV

, the

synchronous rectification feature is disabled.

Overtemperature Protection If die temperature exceeds

approximately 170°C, the Thermal Shutdown function will dis-

able the outputs until the internal temperature falls below the

15°C hysteresis.

Hall State Reporting The FG1 pin is an open drain output

that changes state at each transition of an external Hall element.

The FG2 pin is an open drain output that changes state at each

HAx transition.

Lock Detect Function The IC will evaluate a locked rotor

condition under either of these two different conditions:

• The FG1 signal is not consistently changing.

• The proper commutation sequence is not being followed. The

motor can be locked in a condition in which it toggles between

two specific Hall device states.

Both of these fault conditions are allowed to persist for period

of time, t

lock

. t

lock

is set by capacitor connected to CLD pin. C

produces a triangle waveform (1.67 V peak-to-peak) with fre-

quency linearly related to the capacitor value. t

lock

is defined as

127 cycles of this triangle waveform, or:

lock

= C

× 20 s/μF

After the wait time, t

lock

, has expired, the outputs are disabled,

and the fault is latched. These fault conditions can only be cleared

by any one of the following actions:

• Rising or falling edge on the DIR pin

• VBB UVLO threshold exceeded (during power-up cycle)

• ENB pin held high for > t

lock

/ 2

The Lock Detect function can be disabled by connecting CLD to

GND.

When the A4931 is in Brake mode, the Lock Detect counter is

disabled.

3-Phase Brushless DC Motor Pre-Driver

A4931

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ET Package, 28-Contact QFN

0.25

+0.05

–0.07

0.55

+0.20

–0.10

0.50

0.90 ±0.10

C0.08

29X

SEATING

PLANE

Terminal #1 mark area

Exposed thermal pad (reference only, terminal #1

identifier appearance at supplier discretion)

For Reference Only

(reference JEDEC MO-220VHHD-1)

Dimensions in millimeters

Exact case and lead configuration at supplier discretion within limits shown

Reference land pattern layout (reference IPC7351

QFN50P500X500X100-29V1M);

All pads a minimum of 0.20 mm from all adjacent pads; adjust as

necessary to meet application process requirements and PCB layout

tolerances; when mounting on a multilayer PCB, thermal vias at the

exposed thermal pad land can improve thermal dissipation (reference

EIA/JEDEC Standard JESD51-5)

PCB Layout Reference View

3.15

0.30

0.50

1.15

4.80

5.00 ±0.15

Coplanarity includes exposed thermal pad and terminals

Allegro MicroSystems, LLC reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to

permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that

the information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, LLC assumes no re spon si bil i ty for its

use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

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