7
Figure 12. Tx-out load detection.Figure 11. Tx enable time.
Figure 10. Tx-out harmonic distortion vs. temperature
for dierent values of R
ref
.
-90
-88
-86
-84
-82
-80
-78
-76
-74
-72
-70
-68
-66
-64
-62
-60
R
ref
= 12
R
ref
= 24
R
ref
= 8 k©
-50 -25 0 25 50 75 100
HD - HARMONIC DISTORTION - dBc
HD2
HD3
f = 132 kHz, Gain = -2,
V
Tx-out
= 3.5 V
PP
, R
L
= 50 ©
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R
ref
= 12 k
R
ref
= 24 k
R
ref
= 8 k
- -
T
A
- AMBIENT TEMPERATURE - ˚C
HD2
HD3
HD2
HD3
f = 132 kHz, Gain = -2
V
Tx-out
= 3.5 V
PP
, R
L
= 50
t
Tx-en
2µs/DIV
Tx-en (PIN 2)
2 V/DIV
Tx-out (PIN 8)
1 V/DIV
Tx-out (PIN 8) 0.5 A/DIV
STATUS
(PIN 1)
2 V/DIV
t
th
t
th
2µs/DIV
8
Figure 16. Tx-out harmonic distortion test circuit.
Test Circuit Diagrams
Unless otherwise noted, all test circuits are at T
A
= 25°C, V
CC
= 5 V, sinusoidal waveform input, and signal frequency f =
132 kHz.
Figure 13. Load detection test circuit.
Figure 15. Tx enable/disable time test circuit.
Figure 14. Gain bandwidth product test circuit.
10 k
5 V
1 µF
100 nF
100 nF
20 k
HCPL - 8100/0810
1
2
3
4
5
6
7
8
Status
T x-en
Tx -in
R
ref
GND
GND
V
CC
Tx -out
5 V
100 µF
V
IN
= 1.75 V
PP
24 k
R
ref
SPECTRUM
50
ANALYZER
5 V
100 nF
10 k
SCOPE
100 nF
V
IN
= 1.25 V
PP
HCPL-8100/0810
1
2
3
4
5
6
7
8
Status
Tx -en
Tx -in
R
ref
GND
GND
V
CC
Tx -out
R
ref
20 k
5 V
100 µF
2.5
1 µF
R
L
5 V
10 k
100 nF
1 µF
100 nF
20 k
HCPL-8100/0810
1
2
3
4 5
6
7
8
Status
Tx -en
Tx -in
R
ref
GND
GND
V
CC
Tx -out
5 V
100 µF
V
IN
= 1 V
PP
f = 10 k ~ 10 MHz
24 k
R
ref
V
OUT
50
R
L
100 µF
100 nF
5 V
100 nF
24 k
R
ref
V
OUT
V
IN
= 1.75 V
PP
10 k
HCPL-8100/0810
1
2
3
4
5
6
7
8
St atus
Tx -en
Tx -in
R
ref
GND
GND
V
CC
Tx -out
20 k
PULSE GEN.
V
PULSE
= 5 V,
f
PULSE
1 kHz
Application Information
The HCPL-8100 and HCPL-0810 are designed to work with
various transceivers and can be used with a variety of
modulation methods including ASK, FSK and BPSK. Figure
17 shows a typical application in a powerline modem using
Frequency Shift Keying (FSK) modulation scheme.
Figure 17. Schematic of HCPL-8100 or HCPL-0810 application for FSK modulation scheme.
Table 1. Typical component values
for LC coupling network.
Figure 18. LC coupling network.
GND
Tx
X2
C2
N
L2
L1
L
1 µF
C3
Carrier
Frequency (kHz)
LC Coupling
L2 (µH) C2 (nF)
110 15 150
120 10 220
132 6.8 220
150 6.8 220
N
1 µF
C3
R1
5 V
C2
330 µH
L1
R3
2
F ilter
Gain =
R2 / R1
R2
L2
L
R
ref
24 k
HCPL - 8100/0810
1
2
3
4
5
6
7
8
Status
Tx-en
Tx-in
R
ref
GND
GND
V
CC
Tx -out
PLM
Transceiver
STATUS
TX-EN
TX
D1
C4
100 nF
100 nF
C1
C5
100 µF
X2
Line Driver
The line driver is capable of driving powerline load imped-
ances with output signals up to 4 V
PP
. The internal biasing
of the line driver is controlled externally via a resistor R
ref
connected from pin 4 to ground. The optimum biasing
point value for modulation frequencies up to 150 kHz
is 24 kW. For higher frequency operation with certain
modulation schemes, it may be necessary to reduce the
resistor value to enable compliance with international
regulations.
The output of the line driver is coupled onto the powerline
using a simple LC coupling circuit as shown in Figure
18. Refer to Table 1 for some typical component values.
Capacitor C2 and inductor L1 attenuate the 50/60 Hz
powerline transmission frequency. A suitable value for
L1 can range in value from 200 µH to 1 mH. To reduce the
series coupling impedance at the modulation frequency,
L2 is included to compensate the reactive impedance of
C2. This inductor should be a low resistive type capable
of meeting the peak current requirements. To meet many
regulatory requirements, capacitor C2 needs to be an X2
type. Since these types of capacitors typically have a very
wide tolerance range of 20%, it is recommended to use as
low Q factor as possible for the L2/C2 combination. Using
a high Q coupling circuit will result in a wide tolerance on
the overall coupling impedance, causing potential commu-
nication diculties with low powerline impedances. Occa-
sionally with other circuit congurations, a high Q coupling
arrangement is recommended, e.g., C2 less than 100 nF. In
this case it is normally used as a compromise to lter out
of band harmonics originating from the line driver. This is
not required with the HCPL-8100 or HCPL-0810.

HCPL-8100

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
Buffers & Line Drivers PLC Powerline DAA IC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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