OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

MC100ES6220AE

P1-P3P4-P6P7-P9
MC100ES6220
Rev 4, 04/2005
Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Low Voltage Dual 1:10 Differential
ECL/PECL Clock Fanout Buffer
The MC100ES6220 is a bipolar monolithic differential clock fanout buffer.
Designed for most demanding clock distribution systems, the MC100ES6220
supports various applications that require the distribution of precisely aligned
differential clock signals. Using SiGe technology and a fully differential
architecture, the device offers very low skew outputs and superior digital signal
characteristics. Target applications for this clock driver are high performance
clock distribution in computing, networking and telecommunication systems.
Features
• Two independent 1:10 differential clock fanout buffers
• 130 ps maximum device skew
• SiGe technology
• Supports DC to 1 GHz operation of clock or data signals
• ECL/PECL compatible differential clock outputs
• ECL/PECL compatible differential clock inputs
• Single 3.3 V, –3.3 V, 2.5 V or –2.5 V supply
• Standard 52-lead LQFP package with exposed pad for enhanced thermal
characteristics
• Supports industrial temperature range
• Pin and function compatible to the MC100EP220
• 52-lead Pb-free Package Available
Functional Description
The MC100ES6220 is designed for low skew clock distribution systems and
supports clock frequencies up to 1 GHz. The device consists of two independent
clock fanout buffers. The CLKA and CLKB inputs can be driven by ECL or PECL compatible signals. The input signal of each
clock buffer is distributed to 10 identical, differential ECL/PECL outputs. If V
BB
is connected to the CLKA or CLKB input and
bypassed to GND by a 10 nF capacitor, the MC100ES6220 can be driven by single-ended ECL/PECL signals utilizing the V
BB
bias voltage output.
In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even
if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts
being used on that side should be terminated.
The MC100ES6220 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the
MC100ES6220 supports positive (PECL) and negative (ECL) supplies. The MC100ES6220 is pin and function compatible to the
MC100EP220.
MC100ES6220
LOW VOLTAGE DUAL
1:10 DIFFERENTIAL ECL/PECL
CLOCK FANOUT BUFFER
AE SUFFIX
52-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 1336A-01
TB SUFFIX
52-LEAD LQFP PACKAGE
EXPOSED PAD
CASE 1336A-01
DATA SHEET
MC100ES6220
IDT™ Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES6220
1
Low Voltage Dual 1:10 Differential
ECL/PECL Clock Fanout Buffer
Advanced Clock Drivers Devices
2 Freescale Semiconductor
MC100ES6220
Figure 1. MC100ES6220 Logic Diagram
Figure 2. 52-Lead Package Pinout (Top View)
V
CC
QA0
V
BB
CLKB
V
CC
Fanout Buffer B
Fanout Buffer A
V
EE
V
EE
QA0
QA1
QA1
QA8
QA8
QA9
QA9
QB0
QB0
QB8
QB8
QB1
QB1
QB9
QB9
CLKB
CLKA
CLKA
V
CC
QA5
QA5
QA4
QA4
QA3
QA3
QA2
QA2
QA1
QA1
QA0
QA0
QB2
QB2
QB3
QB3
QB4
QB4
QB5
QB5
QB6
QB6
QB7
QB7
V
CC
QA6
QA7
QA8
QA9
V
CC
V
CC
V
EE
CLKA
CLKA
V
BB
CLKB
CLKB
V
EE
QB9
QB9
QB8
QB8
40
41
42
43
44
45
46
47
48
49
50
51
52
25
24
23
22
21
20
19
18
17
16
15
14
12345678910111213
39 38 37 36 35 34 33 32 31 30 29 28 27
26
MC100ES6220
QA6
QA7
QA8
QA9
QB0
QB0
QB1
QB1
V
CC
QA4
Table 1. Pin Configuration
Pin I/O Type Function
CLKA, CLKA Input ECL/PECL Differential reference clock signal input for fanout buffer A
CLKB, CLKB Input ECL/PECL Differential reference clock signal input for fanout buffer B
QA[0-9], QA[0-9] Output ECL/PECL Differential clock outputs of fanout buffer A
QB[0-9], QB[0-9] Output ECL/PECL Differential clock outputs of fanout buffer B
V
EE
(1)
1. In ECL mode (negative power supply mode), V
EE
is either –3.3 V or –2.5 V and V
CC
is connected to GND (0 V). In PECL mode (positive
power supply mode), V
EE
is connected to GND (0 V) and V
CC
is either +3.3 V or +2.5 V. In both modes, the input and output levels are
referenced to the most positive supply (V
CC
).
Supply Negative power supply
V
CC
Supply Positive power supply. All V
CC
pins must be connected to the positive
power supply for correct DC and AC operation.
V
BB
Output DC Reference voltage output for single ended ECL and PECL operation
MC100ES6220
Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer NETCOM
IDT™ Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES6220
2
Advanced Clock Drivers Devices
Freescale Semiconductor 3
MC100ES6220
Table 2. Absolute Maximum Ratings
(1)
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Symbol Characteristics Min Max Unit Condition
V
CC
Supply Voltage –0.3 3.6 V
V
IN
DC Input Voltage –0.3 V
CC
+ 0.3 V
V
OUT
DC Output Voltage –0.3 V
CC
+ 0.3 V
I
IN
DC Input Current ±20 mA
I
OUT
DC Output Current ±50 mA
T
S
Storage Temperature –65 125 °C
T
FUNC
Functional Temperature Range T
A
= –40 T
J
= +110 °C
Table 3. General Specifications
Symbol Characteristics Min Typ Max Unit Condition
V
TT
Output Termination Voltage V
CC
– 2
(1)
1. Output termination voltage V
TT
= 0 V for V
CC
= 2.5 V operation is supported but the power consumption of the device will increase.
V
MM ESD Protection (Machine Model) 200 V
HBM ESD Protection (Human Body Model) 4000 V
CDM ESD Protection (Charged Device Model) 2000 V
LU Latch-Up Immunity 200 mA
C
IN
Input Capacitance 4.0 pF Inputs
θ
JA
,θ
JC
,
θ
JB
Thermal Resistance (junction-to-ambient,
junction-to-board, junction-to-case)
See Table 8. Thermal Resistance °C/W
T
J
Operating Junction Temperature
(2)
(continuous operation) MTBF = 9.1 years
2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according
to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are
specified up to 110°C junction temperature allowing the MC100ES6220 to be used in applications requiring industrial temperature range. It
is recommended that users of the MC100ES6220 employ thermal modeling analysis to assist in applying the junction temperature
specifications to their particular application.
0 110 °C
MC100ES6220
Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer NETCOM
IDT™ Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES6220
3
P1-P3P4-P6P7-P9

MC100ES6220AE

Mfr. #:
Buy MC100ES6220AE
Manufacturer:
IDT
Description:
Clock Buffer FSL Dual 1-10 Diff LVPECL Fanout Buffer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet