16
2487D–MICRO–6/08
AT89S51
5. At the end of a programming session, RST can be set low to commence normal device
operation.
Power-off sequence (if needed):
1. Set XTAL1 to “L” (if a crystal is not used).
2. Set RST to “L”.
3. Turn V
CC
power off.
Data Polling: The Data
Polling feature is also available in the serial mode. In this mode, during
a write cycle an attempted read of the last byte written will result in the complement of the MSB
of the serial output byte on MISO.
16.2 Serial Programming Instruction Set
The Instruction Set for Serial Programming follows a 4-byte protocol and is shown in the
”Serial Programming Instruction Set” on page 20.
17. Programming Interface – Parallel Mode
Every code byte in the Flash array can be programmed by using the appropriate combination of
control signals. The write operation cycle is self-timed and once initiated, will automatically time
itself to completion.
Most major worldwide programming vendors offer worldwide support for the Atmel AT89 micro-
controller series. Please contact your local programming vendor for the appropriate software
revision.
Notes: 1. Each PROG pulse is 200 ns - 500 ns for Chip Erase.
2. Each PROG
pulse is 200 ns - 500 ns for Write Code Data.
3. Each PROG
pulse is 200 ns - 500 ns for Write Lock Bits.
4. RDY/BSY
signal is output on P3.0 during programming.
5. X = don’t care.
Table 17-1. Flash Programming Modes
Mode V
CC
RST PSEN
ALE/
PROG
EA/
V
PP
P2.6 P2.7 P3.3 P3.6 P3.7
P0.7-0
Data
P2.3-0 P1.7-0
Address
Write Code Data 5V H L
(2)
12V LHHHH D
IN
A11-8 A7-0
Read Code Data 5V H L H H L L L H H D
OUT
A11-8 A7-0
Write Lock Bit 1 5V H L
(3)
12VHHHHH X X X
Write Lock Bit 2 5V H L
(3)
12V H H H L L X X X
Write Lock Bit 3 5V H L
(3)
12V H L H H L X X X
Read Lock Bits
1, 2, 3
5V H L H H H H L H L
P0.2,
P0.3,
P0.4
XX
Chip Erase 5V H L
(1)
12VHLHLL X X X
Read Atmel ID 5V H L H H LLLLL 1EH0000 00H
Read Device ID 5V H L H H LLLLL 51H0001 00H
Read Device ID 5V H L H H LLLLL 06H0010 00H
