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PSMN005-30K,518
P1-P3
P4-P6
P7-P9
P10-P12
P13-P14
PSMN005-30K
All informatio
n provided in thi
s document is su
bject to legal
disclaimers.
© NXP B.V
. 201
1. All rights reserved.
Product data sheet
Rev
. 2 — 22 December 2011
3 of 13
NXP Semiconductors
PSMN005-30K
N-channel T
renchMOS SiliconMAX logic level FET
Fig 1.
Normalized continuous drain curre
nt as a
function of solde
r point temperature
Fig 2.
Normalized tota
l power dissipation as
a
function of solder
point temperature
Fig 3.
Safe operating area; continuou
s and peak drain curren
ts as a function of drain-source voltage
T
sp
(
°
C)
0
200
150
50
100
03aa25
40
80
120
I
der
(%)
0
T
sp
(
°
C)
0
200
150
50
100
03aa17
40
80
120
P
der
(%)
0
003aah006
10
-1
1
10
10
2
10
3
10
-1
1
10
10
2
V
DS
(V)
I
D
(A)
Limit R
DSon
=
V
DS
/ I
D
DC
100
μ
s
10 ms
t
p
=10
μ
s
100 ms
PSMN005-30K
All informatio
n provided in thi
s document is su
bject to legal
disclaimers.
© NXP B.V
. 201
1. All rights reserved.
Product data sheet
Rev
. 2 — 22 December 2011
4 of 13
NXP Semiconductors
PSMN005-30K
N-channel T
renchMOS SiliconMAX logic level FET
5.
Thermal characteristics
T
able 5.
Thermal characteristics
Symbol
Parameter
Conditions
Min
Ty
p
Max
Unit
R
th(j-sp)
thermal resistance from
junction to solder p
oint
mounted on a metal clad
board ;
see
Figure 4
--2
0
K
/
W
Fig 4.
Transie
nt thermal impe
dance from junc
tion to mountin
g base as a fu
nction of
pulse duration
03ah04
10
−
1
1
10
10
2
10
−
4
10
−
3
10
−
2
10
−
1
1
10
single pulse
δ
= 0.5
0.2
0.1
0.05
0.02
t
p
t
p
T
P
t
T
δ
=
Z
th(j-sp)
(K/W)
t
p
(s)
PSMN005-30K
All informatio
n provided in thi
s document is su
bject to legal
disclaimers.
© NXP B.V
. 201
1. All rights reserved.
Product data sheet
Rev
. 2 — 22 December 2011
5 of 13
NXP Semiconductors
PSMN005-30K
N-channel T
renchMOS SiliconMAX logic level FET
6.
Characteristics
T
able 6.
Characteristics
Symbol
Parameter
Conditions
Min
Ty
p
Max
Unit
St
atic characteris
tics
V
(BR)DSS
drain-source
breakdown voltage
I
D
=2
5
0µ
A
;
V
GS
=0V
;
T
j
=
2
5
°
C 3
0
--V
V
GS(th)
gate-source threshold
voltage
I
D
=1m
A
;
V
DS
=V
GS
; T
j
= 150 °C;
see
Figure 8
0
.
5
--V
I
D
=1m
A
;
V
DS
=V
GS
; T
j
=-
5
5°
C
;
see
Figure 8
--3
.
4
V
I
D
=1m
A
;
V
DS
=V
GS
; T
j
=2
5°
C
;
see
Figure 8
1-
3V
I
DSS
drain leakage current
V
DS
=3
0V
;
V
GS
=0V
;
T
j
=
2
5
°
C
--1
µ
A
V
DS
=3
0V
;
V
GS
=0V
;
T
j
=
1
5
0
°
C
--0
.
5
m
A
I
GSS
gate leakage current
V
GS
=2
0V
;
V
DS
=0V
;
T
j
= 25 °C
-
-
100
nA
V
GS
=-
2
0V
;
V
DS
=0V
;
T
j
= 25 °C
-
-
100
nA
R
DSon
drain-source on-state
resistance
V
GS
=4
.
5V
;
I
D
=1
3A
;
T
j
=2
5°
C
;
see
Figure 9
; see
Figure 10
-6
.
6
8
m
Ω
V
GS
=1
0V
;
I
D
=1
5A
;
T
j
=2
5°
C
;
see
Figure 9
; see
Figure 10
-4
.
4
5
.
5
m
Ω
Dynamic ch
aracter
istics
Q
G(tot)
total gate charge
I
D
=2
0A
;
V
DS
=1
5V
;
V
GS
=4
.
5V
;
T
j
=2
5°
C
;
s
e
e
Figure 1
1
-3
4
-n
C
Q
GS
gate-source ch
arge
-
15
-
nC
Q
GD
gate-drain charge
-
14
-
nC
C
iss
input capacitance
V
DS
=2
5V
;
V
GS
= 0 V
; f = 1 MHz;
T
j
=2
5°
C
;
s
e
e
Figure 12
-
3100
-
pF
C
oss
output capacitance
-
605
-
pF
C
rss
reverse transfer
capacit
ance
-
405
-
pF
t
d(on)
turn-on delay time
V
DS
=1
5V
;
R
L
=1
5
Ω
; V
GS
=1
0V
;
R
G(ext)
=6
Ω
; T
j
=2
5°
C
-1
8
-n
s
t
r
rise time
-
16
-
ns
t
d(off
)
turn-off delay ti
me
-
65
-
ns
t
f
fall time
-
45
-
ns
g
fs
transfer conductance
V
DS
=1
5V
;
I
D
=2
0A
;
T
j
=2
5°
C
-
6
0
-
S
Source-drain diod
e
V
SD
source-drain voltage
I
S
=1
5A
;
V
GS
=0V
;
T
j
=2
5°
C
;
see
Figure 13
-
0.81
1.3
V
t
rr
reverse recovery time
I
S
=1
0A
;
d
I
S
/dt
=
-100
A/µs;
V
GS
=0V
;
V
DS
=2
5V
;
T
j
=2
5°
C
-3
5
-n
s
Q
r
recovered charge
-
20
-
nC
P1-P3
P4-P6
P7-P9
P10-P12
P13-P14
PSMN005-30K,518
Mfr. #:
Buy PSMN005-30K,518
Manufacturer:
Nexperia
Description:
RF Bipolar Transistors MOSFET TAPE13 PWR-MOS
Lifecycle:
New from this manufacturer.
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PSMN005-30K,518