Philips Semiconductors Product data
P87C51RA2/RB2/RC2/RD2
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high
speed (30/33 MHz)
2003 Jan 24
31
PX0IP (0B8H)
Priority Bit = 1 assigns high priority
Priority Bit = 0 assigns low priority
BIT SYMBOL FUNCTION
IP.7
IP.6 PPC PCA interrupt priority bit
IP.5 PT2 Timer 2 interrupt priority bit.
IP.4 PS Serial Port interrupt priority bit.
IP.3 PT1 Timer 1 interrupt priority bit.
IP.2 PX1 External interrupt 1 priority bit.
IP.1 PT0 Timer 0 interrupt priority bit.
IP.0 PX0 External interrupt 0 priority bit.
SU01291
PT0PX1PT1PSPT2PPC
01234567
Figure 16. IP Registers
PX0HIPH (B7H)
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
BIT SYMBOL FUNCTION
IPH.7
IPH.6 PPCH PCA interrupt priority bit
IPH.5 PT2H Timer 2 interrupt priority bit high.
IPH.4 PSH Serial Port interrupt priority bit high.
IPH.3 PT1H Timer 1 interrupt priority bit high.
IPH.2 PX1H External interrupt 1 priority bit high.
IPH.1 PT0H Timer 0 interrupt priority bit high.
IPH.0 PX0H External interrupt 0 priority bit high.
SU01292
PT0HPX1HPT1HPSHPT2HPPCH
01234567
Figure 17. IPH Registers
Philips Semiconductors Product data
P87C51RA2/RB2/RC2/RD2
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high
speed (30/33 MHz)
2003 Jan 24
32
Reduced EMI Mode
The AO bit (AUXR.0) in the AUXR register when set disables the
ALE output unless the CPU needs to perform an off-chip memory
access.
Reduced EMI Mode
AUXR (8EH)
765432 1 0
EXTRAM AO
AUXR.1 EXTRAM
AUXR.0 AO
See more detailed description in Figure 32.
Dual DPTR
The dual DPTR structure (see Figure 18) is a way by which the chip
will specify the address of an external data memory location. There
are two 16-bit DPTR registers that address the external memory,
and a single bit called DPS = AUXR1/bit0 that allows the program
code to switch between them.
New Register Name: AUXR1#
SFR Address: A2H
Reset Value: xxxxxxx0B
AUXR1 (A2H)
765 43210
GF2 0 DPS
Where:
DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.
Select Reg DPS
DPTR0 0
DPTR1 1
The DPS bit status should be saved by software when switching
between DPTR0 and DPTR1.
The GF2 bit is a general purpose user-defined flag. Note that bit 2 is
not writable and is always read as a zero. This allows the DPS bit to
be quickly toggled simply by executing an INC AUXR1 instruction
without affecting the GF2 bit.
DPS
DPTR1
DPTR0
DPH
(83H)
DPL
(82H)
EXTERNAL
DATA
MEMORY
SU00745A
BIT0
AUXR1
Figure 18.
DPTR Instructions
The instructions that refer to DPTR refer to the data pointer that is
currently selected using the AUXR1/bit 0 register. The six
instructions that use the DPTR are as follows:
INC DPTR Increments the data pointer by 1
MOV DPTR, #data16 Loads the DPTR with a 16-bit constant
MOV A, @ A+DPTR Move code byte relative to DPTR to ACC
MOVX A, @ DPTR Move external RAM (16-bit address) to
ACC
MOVX @ DPTR , A Move ACC to external RAM (16-bit
address)
JMP @ A + DPTR Jump indirect relative to DPTR
The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See
Application Note AN458
for more details.
Philips Semiconductors Product data
P87C51RA2/RB2/RC2/RD2
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high
speed (30/33 MHz)
2003 Jan 24
33
Programmable Counter Array (PCA)
The Programmable Counter Array available on the
P87C51RA2/RB2/RC2/RD2 is a special 16-bit Timer that has five
16-bit capture/compare modules associated with it. Each of the
modules can be programmed to operate in one of four modes: rising
and/or falling edge capture, software timer, high-speed output, or
pulse width modulator. Each module has a pin associated with it in
port 1. Module 0 is connected to P1.3 (CEX0), module 1 to P1.4
(CEX1), etc. The basic PCA configuration is shown in Figure 19.
The PCA timer is a common time base for all five modules and can
be programmed to run at: 1/6 the oscillator frequency, 1/2 the
oscillator frequency, the Timer 0 overflow, or the input on the ECI pin
(P1.2). The timer count source is determined from the CPS1 and
CPS0 bits in the CMOD SFR as follows (see Figure 22):
CPS1 CPS0 PCA Timer Count Source
0 0 1/6 oscillator frequency (6-clock mode);
1/12 oscillator frequency (12-clock mode)
0 1 1/2 oscillator frequency (6-clock mode);
1/4 oscillator frequency (12-clock mode)
1 0 Timer 0 overflow
1 1 External Input at ECI pin
In the CMOD SFR are three additional bits associated with the PCA.
They are CIDL which allows the PCA to stop during idle mode,
WDTE which enables or disables the watchdog function on
module 4, and ECF which when set causes an interrupt and the
PCA overflow flag CF (in the CCON SFR) to be set when the PCA
timer overflows. These functions are shown in Figure 20.
The watchdog timer function is implemented in module 4 (see
Figure 29).
The CCON SFR contains the run control bit for the PCA and the
flags for the PCA timer (CF) and each module (refer to Figure 23).
To run the PCA the CR bit (CCON.6) must be set by software. The
PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when
the PCA counter overflows and an interrupt will be generated if the
ECF bit in the CMOD register is set, The CF bit can only be cleared
by software. Bits 0 through 4 of the CCON register are the flags for
the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set
by hardware when either a match or a capture occurs. These flags
also can only be cleared by software. The PCA interrupt system
shown in Figure 21.
Each module in the PCA has a special function register associated
with it. These registers are: CCAPM0 for module 0, CCAPM1 for
module 1, etc. (see Figure 24). The registers contain the bits that
control the mode that each module will operate in. The ECCF bit
(CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module)
enables the CCF flag in the CCON SFR to generate an interrupt
when a match or compare occurs in the associated module. PWM
(CCAPMn.1) enables the pulse width modulation mode. The TOG
bit (CCAPMn.2) when set causes the CEX output associated with
the module to toggle when there is a match between the PCA
counter and the module’s capture/compare register. The match bit
MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON
register to be set when there is a match between the PCA counter
and the module’s capture/compare register.
The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5)
determine the edge that a capture input will be active on. The CAPN
bit enables the negative edge, and the CAPP bit enables the positive
edge. If both bits are set both edges will be enabled and a capture will
occur for either transition. The last bit in the register ECOM
(CCAPMn.6) when set enables the comparator function. Figure 25
shows the CCAPMn settings for the various PCA functions.
There are two additional registers associated with each of the PCA
modules. They are CCAPnH and CCAPnL and these are the
registers that store the 16-bit count when a capture occurs or a
compare should occur. When a module is used in the PWM mode
these registers are used to control the duty cycle of the output.
MODULE FUNCTIONS:
16-BIT CAPTURE
16-BIT TIMER
16-BIT HIGH SPEED OUTPUT
8-BIT PWM
WATCHDOG TIMER (MODULE 4 ONLY)
MODULE 0
MODULE 1
MODULE 2
MODULE 3
MODULE 4
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3
P1.7/CEX4
16 BITS
PCA TIMER/COUNTER
TIME BASE FOR PCA MODULES
16 BITS
SU00032
Figure 19. Programmable Counter Array (PCA)

P87C51RD2BA,512

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Microcontrollers - MCU 8-bit Microcontrollers - MCU 80C51 64K/1K OTP
Lifecycle:
New from this manufacturer.
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