Document Number: 38-05328 Rev. *M Page 7 of 18
Switching Characteristics
Over the Operating Range
Parameter
[13]
Description
55 ns 70 ns
Unit
Min Max Min Max
Read Cycle
t
RC
Read cycle time 55 – 70 – ns
t
AA
Address to data valid – 55 – 70 ns
t
OHA
Data hold from address change 10 – 10 – ns
t
ACE
CE
1
LOW and CE
2
HIGH to data valid – 55 – 70 ns
t
DOE
OE LOW to data valid – 25 – 35 ns
t
LZOE
OE LOW to low Z
[14]
5 – 5 – ns
t
HZOE
OE HIGH to high Z
[14, 15]
– 20 – 25 ns
t
LZCE
CE
1
LOW and CE
2
HIGH to low Z
[14]
10 – 10 – ns
t
HZCE
CE
1
HIGH and CE
2
LOW to high Z
[14, 15]
– 20 – 25 ns
t
PU
CE
1
LOW and CE
2
HIGH to power-up 0 – 0 – ns
t
PD
CE
1
HIGH and CE
2
LOW to power-down – 55 – 70 ns
t
DBE
BLE/BHE LOW to data valid – 55 – 70 ns
t
LZBE
BLE/BHE LOW to low Z
[14]
10 – 10 – ns
t
HZBE
BLE/BHE HIGH to high Z
[14, 15]
– 20 – 25 ns
Write Cycle
[16]
t
WC
Write cycle time 55 – 70 – ns
t
SCE
CE
1
LOW and CE
2
HIGH
to write end 40 – 60 – ns
t
AW
Address setup to write end 40 – 60 – ns
t
HA
Address hold from write end 0 – 0 – ns
t
SA
Address setup to write start 0 – 0 – ns
t
PWE
WE pulse width 40 – 45 – ns
t
BW
BLE/BHE LOW to write end 40 – 60 – ns
t
SD
Data setup to write end 25 – 30 – ns
t
HD
Data hold from write end 0 – 0 – ns
t
HZWE
WE LOW to high-Z
[14, 15]
– 20 – 25 ns
t
LZWE
WE HIGH to low-Z
[14]
10 – 10 – ns
Notes
13. Test conditions for all parameters other than Tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of V
CC(typ)
/2, input pulse levels of
0 to V
CC(typ.)
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads and Waveforms” section.
14. At any temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
15. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
16. The internal Write time of the memory is defined by the overlap of WE
, CE
1
= V
IL
, BHE and/or BLE = V
IL
, and CE
2
= V
IH
. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that
terminates the Write.
