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NCP5391MNR2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
NCP5391
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16
TYPICAL CHARACTERISTICS
T
A
, AMBIENT TEMPERATURE (°C)
13.6
13.4
12.6
12.8
13.2
0
13.0
10 20 30 40
I
CC
, IC QUIESCENT CURRENT (mA)
50 60 70
Figure 4. IC Quiescent Current vs. Ambient
Temperature
Figure 5. VCC Undervoltage Lockout
Threshold Voltage vs. Ambient Temperature
Figure 6. Typical DAC Voltage Offset vs.
Temperature
10
9
7
8
V
CC
, UNDERVOLTAGE LOCKOUT
THRESHOLD VOLTAGE (V)
10
T
A
, AMBIENT TEMPERATURE (°C)
0 20 3040506070
V
CC
Increasing Voltage
V
CC
Decreasing Voltage
0.0188
0.0186
0.0182
0.0184
DAC OFFSET
0.0180
0.6
VID
0.5 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4
70°C
0.0198
0.0196
0.0192
0.0194
0.0190
1.5 1.6
25°C
0°C
NCP5391
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17
FUNCTIONAL DESCRIPTION
General
The NCP5391 dual edge modulated multiphase PWM
controller is specifically designed with the necessary
features for a high current VR11 CPU power system. The
IC consists of the following blocks: Precision
Programmable DAC, Differential Remote Voltage Sense
Amplifier, High Performance Voltage Error Amplifier,
Differential Current Feedback Amplifiers, Precision
Oscillator and Triangle Wave Generators, and PWM
Comparators. Protection features include Undervoltage
Lockout, Soft-Start, Overcurrent Protection, Overvoltage
Protection, and Power Good Monitor.
Remote Output Sensing Amplifier (RSA)
A true differential amplifier allows the NCP5391 to
measure Vcore voltage feedback with respect to the Vcore
ground reference point by connecting the Vcore reference
point to VS+, and the Vcore ground reference point to VS-.
This configuration keeps ground potential differences
between the local controller ground and the Vcore ground
reference point from affecting regulation of Vcore between
Vcore and Vcore ground reference points. The RSA also
subtracts the DAC (minus VID offset) voltage, thereby
producing an unamplified output error voltage at the
DIFFOUT pin. This output also has a 1.3 V bias voltage to
allow both positive and negative error voltages.
Precision DAC
A precision programmable DAC is provided. This DAC
has 0.5% accuracy over the entire operating temperature
range of the part.
High Performance Voltage Error Amplifier
The error amplifier is designed to provide high slew rate
and bandwidth. Although not required when operating as
a voltage regulator, a capacitor from COMP to VFB is
required for stable unity gain test configurations.
Gate Driver Outputs and 2/3 Phase Operation
The part can be configured to run in 2- or 3-phase mode.
In 2-phase mode, phases 1 and 3 should be used to drive the
external gate drivers as shown in the 2-phase Applications
Schematic. In 2-phase mode, gate output G2 must be
grounded as shown in the 2-phase Applications Schematic.
The following truth table summarizes the modes of
operation:
Mode
Gate Output Connections
G1 G2 G3
2-Phase Normal GND Normal
3-Phase Normal Normal Normal
These are the only allowable connection schemes to
program the modes of operation.
Differential Current Sense Amplifiers
Three differential amplifiers are provided to sense the
output current of each phase. The inputs of each current
sense amplifier must be connected across the current
sensing element of the phase controlled by the
corresponding gate output (G1, G2 or G3). If 2 phase is
unused, the differential inputs to that phase's current
sense amplifier must be shorted together and connected
to V
CCP
as shown in the 2-phase Application
Schematics.
A voltage is generated across the current sense element
(such as an inductor or sense resistor) by the current
flowing in that phase. The output of the current sense
amplifiers are used to control three functions. First, the
output controls the adaptive voltage positioning, where the
output voltage is actively controlled according to the
output current. In this function, all of the current sense
outputs are summed so that the total output current is used
for output voltage positioning. Second, the output signal is
fed to the current limit circuit. This again is the summed
current of all phases in operation. Finally, the individual
phase current is connected to the PWM comparator. In this
way current balance is accomplished.
Oscillator and Triangle Wave Generator
A programmable precision oscillator is provided. The
oscillator's frequency is programmed by the resistance
connected from the ROSC pin to ground. The user will
usually form this resistance from two resistors in order to
create a voltage divider that uses the ROSC output voltage
as the reference for creating the current limit setpoint
voltage. The oscillator frequency range is 100 kHz/phase
to 1.0 MHz/phase. The oscillator generates up to 3 triangle
waveforms (symmetrical rising and falling slopes)
between 1.3 V and 2.3 V. The triangle waves have a phase
delay between them such that for 2-, 3-phase operation the
PWM outputs are separated by 180 and 120 angular
degrees, respectively.
NCP5391
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18
PWM Comparators with Hysteresis
Three PWM comparators receive the error amplifier
output signal at their noninverting input. Each comparator
receives one of the triangle waves offset by 1.3 V at it's
inverting input. The output of the comparator generates the
PWM outputs G1, G2 and G3.
During steady state operation, the duty cycle will center
on the valley of the triangle waveform, with steady state
duty cycle calculated by V
out
/V
in
. During a transient event,
both high and low comparator output transitions shift phase
to the points where the error amplifier output intersects the
down and up ramp of the triangle wave.
PROTECTION FEATURES
Undervoltage Lockout
An undervoltage lockout (UVLO) senses the VCC input.
During powerup, the input voltage to the controller is
monitored, and the PWM outputs and the soft-start circuit
are disabled until the input voltage exceeds the threshold
voltage of the UVLO comparator. The UVLO comparator
incorporates hysteresis to avoid chattering, since VCC is
likely to decrease as soon as the converter initiates
soft-start.
Overcurrent Shutdown
A programmable overcurrent function is incorporated
within the IC. A comparator and latch makeup this
function. The inverting input of the comparator is
connected to the ILIM pin. The voltage at this pin sets the
maximum output current the converter can produce. The
ROSC pin provides a convenient and accurate reference
voltage from which a resistor divider can create the
overcurrent setpoint voltage. Although not actually
disabled, tying the ILIM pin directly to the ROSC pin sets
the limit above useful levels – effectively disabling
overcurrent shutdown. The comparator noninverting input
is the summed current information from the current sense
amplifiers. The overcurrent latch is set when the current
information exceeds the voltage at the ILIM pin. The
outputs are immediately disabled, the VR_RDY and
DRVON pins are pulled low, and the soft-start is pulled
low. The outputs will remain disabled until the V
CC
voltage
is removed and re-applied, or the ENABLE input is
brought low and then high.
Overvoltage Protection and Power Good Monitor
An output voltage monitor is incorporated. During
normal operation, if the voltage at the DIFFOUT pin
exceeds 1.3 V, the VR_RDY pin goes low, the DRVON
signal remains high, the PWM outputs are set low. The
outputs will remain disabled until the V
CC
voltage is
removed and reapplied. During normal operation, if the
output voltage falls more than 300 mV below the DAC
setting, the VR_RDY pin will be set low until the output
rises.
Soft-Start
The NCP5391 incorporates an externally programmable
soft-start. The soft-start circuit works by controlling the
ramp-up of the DAC voltage during powerup. The initial
soft-start pin voltage is 0 V. The soft-start circuitry clamps
the DAC input of the Remote Sense Amplifier to the SS pin
voltage until the SS pin voltage exceeds the DAC setting
minus VID offset. The soft-start pin is pulled to 0 V if there
is an overcurrent shutdown, if the ENABLE pin is low, if
V
CC
is below the UVLO threshold, or if an overvoltage
condition exists.
The NCP5391 ramps Vcore to 1.1 V at the SS capacitor
charge rate, pauses at 1.1 V for 170 s, reads the VID pins
to determine the DAC setting, then ramps Vcore to the
final DAC setting at the Dynamic VID slew rate of 7.3
mV/s. Typical soft- start sequence is shown in the
following graph.
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
VOLTAGE
0
TIME
VID Setting
Vcore Voltage
SS Pin Voltage
Boot
Dwell Time
NCP5391
Internal Dynamic
VID Rate Limit
Boot Voltage
Figure 7. Typical VR11 Soft-Start Sequence to Vcore = 1.3 V
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NCP5391MNR2G

Mfr. #:
Buy NCP5391MNR2G
Manufacturer:
ON Semiconductor
Description:
IC REG CTRLR INTEL 3OUT 32QFN
Lifecycle:
New from this manufacturer.
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