10
LTC1702A
1702afa
Figure 2. Floating TG Driver Supply
amp of continuous current with peak currents up to 5A to
slew large MOSFET gates quickly. The external MOSFETs
are connected with the drain of QT attached to the input
supply and the source of QT at the switching node SW. QB
is the synchronous rectifier with its drain at SW and its
source at PGND. SW is connected to one end of the
inductor, with the other end connected to V
OUT
. The output
capacitor is connected from V
OUT
to PGND.
When a switching cycle begins, QB is turned off and QT is
turned on. SW rises almost immediately to V
IN
and the
inductor current begins to increase. When the PWM pulse
finishes, QT turns off and one nonoverlap interval later, QB
turns on. Now SW drops to PGND and the inductor current
decreases. The cycle repeats with the next tick of the
master clock. The percentage of time spent in each mode
is controlled by the duty cycle of the PWM signal, which in
turn is controlled by the feedback amplifier. The master
clock generates a 1V
P-P
, 550kHz sawtooth waveform and
turns QT once every 1.8µs. In a typical application with a
5V input and a 1.6V output, the duty cycle will be set at 1.6/
5 × 100% or 32% by the feedback loop. This will give
roughly a 575ns on-time for QT and a 1.22µs on-time for
QB.
This constant frequency operation brings with it a couple
of benefits. Inductor and capacitor values can be chosen
with a precise operating frequency in mind and the feed-
APPLICATIONS INFORMATION
WUU
U
back loop components can be similarly tightly specified.
Noise generated by the circuit will always be in a known
frequency band with the 550kHz frequency designed to
leave the 455kHz IF band free of interference. Subharmonic
oscillation and slope compensation, common headaches
with constant frequency current mode switchers, are
absent in voltage mode designs like the LTC1702A.
During the time that QT is on, its source (the SW pin) is at
V
IN
. V
IN
is also the power supply for the LTC1702A. How-
ever, QT requires V
IN
+ V
GS(ON)
at its gate to achieve
minimum R
ON
. This presents a problem for the
LTC1702A— it needs to generate a gate drive signal at TG
higher than its highest supply voltage. To get around this,
the TG driver runs from floating supplies, with its negative
supply attached to SW and its power supply at BOOST.
This allows it to slew up and down with the source of QT.
In combination with a simple external charge pump (Fig-
ure 2), this allows the LTC1702A to completely enhance
the gate of QT without requiring an additional, higher
supply voltage.
The two channels of the LTC1702A run from a common
clock, with the phasing chosen to be 180° from side 1 to
side 2. This has the effect of doubling the frequency of the
switching pulses seen by the input bypass capacitor, sig-
nificantly lowering the RMS current seen by the capacitor
and reducing the value required (see the 2-Phase section).
+
TG
BOOST
SW
BG
PGND
PV
CC
D
CP
C
IN
+
C
OUT
1702A F02
V
OUT
L
EXT
V
IN
QT
QB
C
CP
1µF
LTC1702A
