P1708CF-08SR

P1708C
Notebook LCD Panel EMI
Reduction IC
©2010 SCILLC. All rights reserved. Publi
cation Order Number:
NOVEMB&R 2010 – Rev. 2.1 P1708/D
Features
FCC approved method of EMI attenuation.
Gen
erates a low EMI spread spectrum clock of the
input frequency.
Optimized for frequency range from 50 to 110MHz.
Internal loop filter minimizes external components and
board space.
Four selectable spread ranges.
Low inherent cycle-to-cycle jitter.
3.3V operating voltage range.
TTL or CMOS compatible inputs and outputs.
CMOS design.
o 8.46mA @ 3.3V, 54MHz
o 9.79mA @ 3.3V, 65MHz
o 12.06mA @ 3.3V, 81MHz
o 16.51mA @ 3.3V, 108MHz
Supports notebook VGA and other LCD timing
controller applications.
Pinout compatible to ICS MK1708 and Cypress
CY25560.
SSON / SBM pin for Spread Spectrum On/Off and
Standby Mode controls.
Available in 8-pin SOIC and TSSOP.
Product Description
The P1708C is a versatile spread spectrum frequency
modulator designed specifically for input clock frequencies.
The P1708C reduces electromagnetic interference (EMI) at
the clock source, allowing system wide reduction of EMI of
down stream clock and data dependent signals. The
P1708C allows significant system cost savings by reducing
the number of circuit board layers, ferrite beads, shielding,
and other passive components that are traditionally
required to pass EMI regulations.
The P1708C modulates the output of a single PLL in order
to “spread” the bandwidth of a synthesized clock, and more
importantly, decreases the peak amplitudes of its
harmonics. This result in significantly lower system EMI
compared to the typical narrow band signal produced by
oscillators and most frequency generators. Lowering EMI
by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation.’
The P1708C uses the most efficient and optimized
modul
ation profile approved by the FCC and is
implemented in a proprietary all digital method.
Applications
The P1708C is targeted towards notebook LCD displays,
and other displays using an LVDS interface, PC peripheral
devices, and embedded systems.
Block Diagram
VSS
CLKIN
Feedback
Divider
Modulation
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
PLL
VDD
SSON
SR0
SR1
Frequency
Divider
P1708C
Rev. 2 | Page 2 of 7 | www.onsemi.com
SSON/SBM
Pin Configuration
Pin Description
Pin# Pin Name Type Description
1 CLKIN I
Connect to externally generated clock signal. To put the part into standby mode,
disable the input clock signal to this pin and pull SSON / SBM (pin 5) low. Refer to
Standby Mode Selection Table.
2 VDD P Connect to +3.3V.
3 VSS P Ground Connection. Connect to system ground.
4 ModOUT O Spread spectrum clock output.
5 SSON / SBM I
Spread Spectrum On/Off and standby mode control. Refer to Standby Mode
Selection Table. This pin has an internal pull-up resistor.
6 SR1 I
Digital logic input used to select Spreading Range. Refer to Spread Spectrum
Selection Table. This pin has an internal pull-up resistor.
7 SR0 I
Digital logic input used to select Spreading Range. Refer to Spread Spectrum
Selection Table. This pin has an internal pull-up resistor.
8 NC - No connect.
Standby Mode Selection
CLKIN SSON / SBM
Spread
Spectrum
ModOUT PLL Mode
Disabled 0 N/A Disabled Disabled Standby
Disabled 1 N/A Disabled Free Running Free Running
Enabled 0 Off Reference Disabled Buffer out
Enabled 1 On Normal Normal Normal
1
2
3
4
5
6
7
8
P1708C
CL
KIN
VDD
VSS
ModOUT
SR1
SR0
NC
P1708C
Rev. 2 | Page 3 of 7 | www.onsemi.com
Spread Range Selection
SR1 SR0 Spreading Range Modulation Rate
0 0 ±1.00% (F
IN
/40) * 62.49KHz
0 1 ±2.00% (F
IN
/40) * 62.49KHz
1 0 ±0.25% (F
IN
/40) * 62.49KHz
1 1 ±0.75% (F
IN
/40) * 62.49KHz
Schematic for Notebook VGA Application
Note: To set the P1708C to standby mode, disable the input clock (pin 1 CLKIN) and pull SSON (pin 5) low. Refer to Standby Mode
Selection Table.
Absolute Maximum Ratings
Symbol Parameter Rating Unit
VDD, V
IN
Voltage on any pin with respect to Ground -0.5 to +7.0 V
T
STG
Storage temperature -65 to +125 °C
T
s
Max. Soldering Temperature (10 sec) 260 °C
T
J
Junction Temperature 150 °C
T
DV
Static Discharge Voltage (As per JEDEC STD22- A114-B)
2 KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Operating Conditions
Parameter Description Min Max Unit
VDD Supply Voltage 2.7 3.7 V
T
A
Operating Temperature (Ambient Temperature) -40
+85
°C
C
Load Capacitance 15 pF
C
IN
Input Capacitance 7 pF
Pin 8 can be tied either high or low,
or
it can be left unconnected.
Tie SR0 and SR1 high / low
according to spread range desired.
External resistors are not needed to
pull these pins high.
Pin 5 SSON should be left unconnected to turn on
spread spectrum. Pull this pin low to turn spread
spectrum OFF and enable stand-by mode.
50MHz to 110MHz pixel clock input
from VGA chip.
FB
VDD
0.1µF
1
2
4
3
8
7
5
6
CLKIN
VDD
VSS
ModOUT
SSON
SR1
SR0
NC
P1708C
50MHz to 110MHz Pixel Clock
Input from VGA Chip.

P1708CF-08SR

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Generators & Support Products 50-110MHZ 3.3V GP EMI
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet