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ATF-55143-TR1G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
ATF-55143
Low Noise Enhancement Mode Pseudomorphic HEMT
in a Surface Mount Plastic Package
Data Sheet
Description
Avago Technologies’ ATF-55143 is a high dynamic range,
very low noise, single supply E-PHEMT housed in a
4-lead SC-70 (SOT-343) surface mount plastic package.
The combination of high gain, high linearity and low
noise makes the ATF-55143 ideal for cellular/PCS hand-
sets, wireless data systems (WLL/RLL, WLAN and MMDS)
and other systems in the 450 MHz to 6 GHz frequency
range.
Surface Mount Package SOT-343
Features
High linearity performance
Single Supply Enhancement Mode Technology
[1]
Very low noise  gure
Excellent uniformity in product speci cations
400 micron gate width
Low cost surface mount small plastic package SOT-
343 (4 lead SC-70)
Tape-and-Reel packaging option available
Lead Free Option Available
Speci cations
2 GHz; 2.7V, 10 mA (Typ.)
24.2 dBm output 3
rd
order intercept
14.4 dBm output power at 1 dB gain compression
0.6 dB noise  gure
17.7 dB associated gain
Lead-free option available
Applications
Low noise ampli er for cellular/PCS handsets
LNA for WLAN, WLL/RLL and MMDS applications
General purpose discrete E -PHEMT for other ultra low
noise applications
Note:
1. Enhancement mode technology requires positive Vgs, thereby
eliminating the need for the negative gate voltage associated with
conventional depletion mode devices.
Pin Connections and Package Marking
SOURCE
DRAIN
GATE
SOURCE
5Fx
Note:
Top View. Package marking provides orientation and identi cation
“5F” = Device Code
“x” = Date code character identi es month of manufacture.
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model (Class A)
ESD Human Body Model (Class 0)
Refer to Avago Application Note A004R:
Electrostatic Discharge Damage and Control.
2
ATF-55143 Absolute Maximum Ratings
[1]
Absolute
Symbol Parameter Units Maximum
V
DS
Drain-Source Voltage
[2]
V 5
V
GS
Gate-Source Voltage
[2]
V -5 to 1
V
GD
Gate Drain Voltage
[2]
V -5 to 1
I
DS
Drain Current
[2]
mA 100
I
GS
Gate Current
[5]
mA 1
P
diss
Total Power Dissipation
[3]
mW 270
P
in max.
RF Input Power
[5]
(Vds=2.7V, Ids=10mA) dBm 10
(Vds=0V, Ids=0mA) dBm 10
T
CH
Channel Temperature °C 150
T
STG
Storage Temperature °C -65 to 150

jc
Thermal Resistance
[4]
°C/W 235
ESD (Human Body Model) V 200
ESD (Machine Model) V 25
Notes:
1. Operation of this device above any one of these parameters may
cause permanent damage.
2. Assumes DC quiescent conditions.
3. Source lead temperature is 25°C. Derate 4.3 mW/°C for T
L
> 87°C.
4. Thermal resistance measured using 150°C Liquid Crystal Measure-
ment method.
5. Device can safely handle +10 dBm RF Input Power as long as I
GS
is
limited to 1 mA. I
GS
at P
1dB
drive level is bias circuit dependent. See
applications section for additional information.
Product Consistency Distribution Charts
[6, 7]
V
DS
(V)
Figure 1. Typical I-V Curves.
(V
GS
= 0.1 V per step)
I
DS
(mA)
0.4V
0.3V
0.5V
0.6V
0.7V
02146537
70
60
50
40
30
20
10
0
OIP3 (dBm)
Figure 2. OIP3 @ 2.7 V, 10 mA.
LSL = 22.0, Nominal = 24.2
22 23 2524 26
300
250
200
150
100
50
0
Cpk = 2.02
Stdev = 0.36
-3 Std
GAIN (dB)
Figure 3. Gain @ 2.7 V, 10 mA.
USL = 18.5, LSL = 15.5, Nominal = 17.7
15 1716 18 19
200
160
120
80
40
0
Cpk = 1.023
Stdev = 0.28
-3 Std +3 Std
NF (dB)
Figure 4. NF @ 2.7 V, 10 mA.
USL = 0.9, Nominal = 0.6
0.43 0.630.53 0.830.73 0.93
240
200
160
120
80
40
0
Cpk = 3.64
Stdev = 0.031
+3 Std
Notes:
6. Distribution data sample size is 500 samples taken from 6 di erent wafers. Future wafers allocated to this product may have nominal values
anywhere between the upper and lower limits.
7. Measurements made on production test board. This circuit represents a trade-o between an optimal noise match and a realizeable match
based on production test equipment. Circuit losses have been de-embedded from actual measurements.
3
ATF-55143 Electrical Speci cations
T
A
= 25°C, RF parameters measured in a test circuit for a typical device
Symbol Parameter and Test Condition Units Min. Typ.
[2]
Max.
Vgs
Operational Gate Voltage Vds = 2.7V, Ids = 10 mA V 0.3 0.47 0.65
Vth
Threshold Voltage Vds = 2.7V, Ids = 2 mA V 0.18 0.37 0.53
Idss
Saturated Drain Current Vds = 2.7V, Vgs = 0V μA — 0.1 3
Gm
Transconductance Vds = 2.7V, gm = Idss/Vgs; mmho 110 220 285
Vgs = 0.75 –0.7 = 0.05V
Igss Gate Leakage Current Vgd = Vgs = -2.7V μA — — 95
NF Noise Figure
[1]
f = 2 GHz Vds = 2.7V, Ids = 10 mA dB — 0.6 0.9
f = 900 MHz Vds = 2.7V, Ids = 10 mA dB — 0.3 —
Ga Associated Gain
[1]
f = 2 GHz Vds = 2.7V, Ids = 10 mA dB 15.5 17.7 18.5
f = 900 MHz Vds = 2.7V, Ids = 10 mA dB — 21.6 —
OIP3
Output 3
rd
Order f = 2 GHz Vds = 2.7V, Ids = 10 mA dBm 22.0 24.2 —
Intercept Point
[1]
f = 900 MHz Vds = 2.7V, Ids = 10 mA dBm — 22.3 —
P1dB
1dB Compressed f = 2 GHz Vds = 2.7V, Ids = 10 mA dBm — 14.4 —
Output Power
[1]
f = 900 MHz Vds = 2.7V, Ids = 10 mA dBm — 14.2 —
Notes:
1. Measurements obtained using production test board described in Figure 5.
2. Typical values determined from a sample size of 500 parts from 6 wafers.
Input
50 Ohm
Transmission
Line Including
Gate Bias T
(0.3 dB loss)
Input
Matching Circuit
Γ_mag = 0.4
Γ_ang = 83°
(0.3 dB loss)
Output
Matching Circuit
Γ_mag = 0.5
Γ_ang = -26°
(1.2 dB loss)
DUT
50 Ohm
Transmission
Line Including
Drain Bias T
(0.3 dB loss)
Output
Figure 5. Block diagram of 2 GHz production test board used for Noise Figure, Associated Gain, P1dB, OIP3, and IIP3 measurements. This circuit represents a trade-o between
an optimal noise match, maximum OIP3 match and associated impedance matching circuit losses. Circuit losses have been de-embedded from actual measurements.
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ATF-55143-TR1G

Mfr. #:
Buy ATF-55143-TR1G
Manufacturer:
Broadcom / Avago
Description:
RF JFET Transistors Transistor GaAs Single Voltage
Lifecycle:
New from this manufacturer.
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