2005-2013 Microchip Technology Inc. DS21937B-page 9
TC4423M/TC4424M/TC4425M
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Input A (IN A)
IN A is a TTL/CMOS-compatible input that controls
OUT A. This input has 300 mV of hysteresis between
the high and low input levels that allows it to be driven
from slow rising and falling signals, as well as providing
noise immunity.
3.2 Input B (IN B)
IN B is a TTL/CMOS-compatible input that controls
OUT B. This input has 300 mV of hysteresis between
the high and low input levels that allows it to be driven
from slow rising and falling signals, as well as providing
noise immunity.
3.3 Output B (OUT B)
OUT B is a CMOS push-pull output that is capable of
sourcing and sinking 3A peaks of current (V
DD
= 18V).
The low output impedance ensures the gate of the
external MOSFET will stay in the intended state even
during large transients. This output also has a reverse
current latch-up rating of 1.5A.
3.4 Output A (OUT A)
OUT A is a CMOS, push-pull output that is capable of
sourcing and sinking 3A peaks of current (V
DD
= 18V).
The low output impedance ensures the gate of the
external MOSFET will stay in the intended state even
during large transients. This output also has a reverse
current latch-up rating of 1.5A.
3.5 Supply Input (V
DD
)
V
DD
is the bias supply input for the MOSFET driver and
has a voltage range of 4.5V to 18V. This input must be
decoupled to ground with a local ceramic capacitor.
This bypass capacitor provides a localized low-
impedance path for the peak currents that are to be
provided to the load.
3.6 Ground (GND)
GND is the device return pin. The ground pin(s) should
have a low-impedance connection to the bias supply
source return. High peak currents will flow out the
ground pin(s) when the capacitive load is being
discharged.
8-Pin
CERDIP
Symbol Description
1 NC No connection
2 IN A Input A
3 GND Ground
4 IN B Input B
5 OUT B Output B
6V
DD
Supply input
7 OUT A Output A
8 NC No connection
