9
LTC3406-1.2
340612fa
APPLICATIO S I FOR ATIO
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1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the electrical character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge, dQ, moves from V
IN
to ground. The resulting
dQ/dt is the current out of V
IN
that is typically larger than
the DC bias current. In continuous mode, I
GATECHG
=
f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate charges of the
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to V
IN
and thus
their effects will be more pronounced at higher supply
voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
(2)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Charateristics
curves. Thus, to obtain I
2
R losses, simply add R
SW
to
R
L
and multiply the result by the square of the average
output current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for less
than 2% total additional loss.
Thermal Considerations
In most applications the LTC3406
-1.2
does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC3406
-1.2
is running at high ambient tem-
perature with low supply voltage, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150°C,
both power switches will be turned off and the SW node
will become high impedance.
To avoid the LTC3406-1.2 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T
R
= (P
D
)(θ
JA
)
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
As an example, consider the LTC3406-1.2 with an input
voltage of 2.7V, a load current of 600mA and an ambient
temperature of 70°C. From the typical performance graph
of switch resistance, the R
DS(ON)
at 70°C is approximately
0.52Ω for the P-channel switch and 0.42Ω for the
N-channel switch. Using equation (2) to find the series
resistance looking into the SW pin gives:
R
SW
= 0.52Ω(0.44) + 0.42Ω(0.56) = 0.46Ω
Therefore, power dissipated by the part is:
P
D
= I
LOAD
2
• R
SW
= 165.6mW
For the SOT-23 package, the θ
JA
is 250°C/W. Thus, the
junction temperature of the regulator is:
T
J
= 70°C + (0.1656)(250) = 111.4°C
which is below the maximum junction temperature of
125°C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R
SW
).
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to (∆I
LOAD
• ESR), where ESR is the effective series
resistance of C
OUT
. ∆I
LOAD
also begins to charge or
discharge C
OUT
, which generates a feedback error signal.
