5T9950PFGI8

1
INDUSTRIAL TEMPERATURE RANGE
IDT5T9950/A
2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
OCTOBER 2008
2002 Integrated Device Technology, Inc. DSC 5869/6c
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Ref input is 3.3V tolerant
4 pairs of programmable skew outputs
Low skew: 185ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Input frequency:
Std: 6MHz to 160MHz
A: 6MHz to 200MHz
Output frequency:
Std: 6MHz to 160MHz
A: 6MHz to 200MHz
2x, 4x, 1/2, and 1/4 outputs
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <100ps cycle-to-cycle
Standard and A speed grades
Available in TQFP package
FUNCTIONAL BLOCK DIAGRAM
sOE
1Q
0
Skew
Select
1Q1
1F1:0
3
3
2Q0
Skew
Select
2Q1
2F1:0
FS
3
REF
PLL
FB
3
3
3Q0
Skew
Select
3Q1
3F1:0
3
3
4Q0
4Q1
Skew
Select
4F1:0
3
3
PE TEST
3
IDT5T9950/A
2.5V PROGRAMMABLE
SKEW PLL CLOCK DRIVER
TURBOCLOCK™ II JR.
DESCRIPTION:
The IDT5T9950 is a high fanout 2.5V PLL based clock driver intended
for high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or lag
the REF input signal. The IDT5T9950 has eight programmable skew
outputs in four banks of 2. Skew is controlled by 3-level input signals that
may be hard-wired to appropriate high-mid-low levels.
When the sOE pin is held low, all the outputs are synchronously enabled.
However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are
synchronously disabled. The LOCK output asserts to indicate when Phase
Lock has been achieved.
Furthermore, when PE is held high, all the outputs are synchronized with
the positive edge of the REF clock input. When PE is held low, all the outputs
are synchronized with the negative edge of REF. The IDT5T9950 has
LVTTL outputs with 12mA balanced drive outputs.
2
INDUSTRIAL TEMPERATURE RANGE
IDT5T9950/A
2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
PIN CONFIGURATION
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Description Max Unit
VDDQ, VDD Supply Voltage to Ground –0.5 to +4.6 V
VI DC Input Voltage –0.5 to VDD+0.5 V
REF Input Voltage –0.5 to +4.6 V
Maximum Power T
A = 85°C 0.7 W
Dissipation TA = 55°C 1.1
T
STG Storage Temperature Range –65 to +150 ° C
NOTE:
1. Capacitance applies to all inputs except TEST, FS, nF[1:0], and DS[1:0].
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Parameter Description Typ. Max. Unit
CIN Input Capacitance 5 7 pF
31
10
3
Q
1
30 29 28 27 26 25
11 12 13 14 15 16
F
S
R
E
F
G
N
D
T
E
S
T
2
F
1
3
Q
0
F
B
2
Q
1
2
Q
0
V
D
D
Q
V
D
D
Q
V
D
D
32
9
3
F
0
G
N
D
2
F
0
1
2
3
4
5
6
7
8
3F
1
4F0
4F1
PE
4Q
1
4Q0
GND
V
DDQ
18 GND
24
23
22
21
20
19
sOE
1F1
1F0
1Q0
1Q1
VDDQ
17 GND
TQFP
TOP VIEW
NOTE:
1. When TEST = MID and sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in
effect unless nF[1:0] = LL.
PIN DESCRIPTION
Pin Name Type Description
REF I N Reference Clock Input
FB I N Feedback Input
TEST
(1)
I N When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control Summary
Table) remain in effect. Set LOW for normal operation.
sOE
(1)
I N Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE = H) - 2Q0 and 2Q1 may
be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE is HIGH, the nF[
1:0] pins act as output
disable controls for individual banks when nF[1:0] = LL. Set sOE LOW for normal operation (has internal pull-down).
P E I N Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference
clock (has internal pull-up).
nF[1:0] IN 3-level inputs for selecting 1 of 9 skew taps or frequency functions
FS I N Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.)
nQ[1:0] OUT Four banks of two outputs with programmable skew
VDDQ PWR Power supply for output buffers
VDD PWR Power supply for phase locked loop, lock output, and other internal circuitry
GND PWR Ground
3
INDUSTRIAL TEMPERATURE RANGE
IDT5T9950/A
2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
Output skew with respect to the REF input is adjustable to compensate
for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timing relationships between clocked compo-
nents. Skew is selectable as a multiple of a time unit (tU) which ranges
from 782ps to 1.5625ns for Standard version and 6.25ps to 1.3ns for A
version (see Programmable Skew Range and Resolution Table). There
are nine skew configurations available for each output pair. These con-
figurations are chosen by the nF1:0 control pins. In order to minimize the
number of control pins, 3-level inputs (HIGH-MID-LOW) are used, they
are intended for but not restricted to hard-wiring. Undriven 3-level in-
puts default to the MID level. Where programmable skew is not a re-
quirement, the control pins can be left open for the zero skew default
setting. The Control Summary Table shows how to select specific skew
taps by using the nF1:0 control pins.
PROGRAMMABLE SKEW
EXTERNAL FEEDBACK
By providing external feedback, the IDT5T9950 gives users flexibility
with regard to skew adjustment. The FB signal is compared with the
input REF signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
NOTES:
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q1:0, 2Q1:0, and
the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the output connected
to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for frequency multiplication by using a divided
output as the FB input.
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example
if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range
applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest FNOM value.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
IDT5T9950 IDT5T9950A
FS = LOW FS = MID FS = HIGH FS = LOW FS = MID FS = HIGH Comments
Timing Unit Calculation (tU) 1/(32 x FNOM) 1/(16 x FNOM) 1/(8 x FNOM) 1/(32 x FNOM) 1/(16 x FNOM) 1/(8 x FNOM)
VCO Frequency Range (FNOM)
(1,2)
24 to 40MHz 40 to 80MHz 80 to 160MHz 24 to 50MHz 48 to 100MHz 96 to 200MHz
Skew Adjustment Range
(3)
Max Adjustment: ±7.8125ns ±9.375ns ±9.375ns ±7.8125ns ±7.8125ns ±7.8125ns ns
±67.5° ±135° ±270° ±67.5° ±135° ±270° Phase Degrees
±18.75% ±37.5% ±75% ±18.75% ±37.5% ±75% % of Cycle Time
Example 1, FNOM = 25MHz tU = 1.25ns tU = 1.25ns
Example 2, FNOM = 37.5MHz tU = 0.833ns tU = 0.833ns
Example 3, FNOM = 50MHz tU = 1.25ns tU = 0.625ns tU = 1.25ns
Example 4, FNOM = 75MHz tU = 0.833ns tU = 0.833ns
Example 5, FNOM = 100MHz tU = 1.25ns tU = 0.625ns tU = 1.25ns
Example 6, FNOM = 150MHz tU = 0.833ns tU = 0.833ns
Example 7, FNOM = 200MHz tU = 0.625ns
PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE

5T9950PFGI8

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 2.5V Turbo Clock II Jr.
Lifecycle:
New from this manufacturer.
Delivery:
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