WM8725 Production Data
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PD, Rev 4.3, February 2012
6
PIN DESCRIPTION
PIN NAME TYPE DESCRIPTION
1
LRCIN Digital input Sample rate clock input
2
DIN Digital input Serial data input
3
BCKIN Digital input Bit clock input
4
NC No connect No internal connection
5
CAP Analogue output Analogue internal reference
6
VOUTR Analogue output Right channel DAC output
7
GND Supply 0V supply
8
VDD Supply Positive supply
9
VOUTL Analogue output Left channel DAC output
10
MUTE Digital input Mute control, high = muted. Internal pull-down
11
NC No connect No internal connection
12
DEEMPH Digital input De-emphasis select, high = de-emphasis ON. Internal pull-up
13
FORMAT Digital input Data input format select, low = normal, high = I
2
S. Internal pull-up
14
SCKI Digital input System clock input (256fs or 384fs)
INTERNAL POWER ON RESET
The WM8725 includes an internal power-on reset circuit. This is shown in Figure 1.This reset
circuit is used to reset the digital logic into a default state after power up.
Figure 1 Internal Power on Reset Circuit
The timing of the power on reset is shown in Figure 2 The circuit monitors VDD and VMID
(CAP pin) and asserts PORB low when VMID is below the minimum threshold Vpor. It is
assumed that VMID will rise slower than VCC due to the capacitor on VMID.
