LT1170/LT1171/LT1172
10
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operaTion
Care should be taken for miniDIP applications to ensure that
the worst case input voltage and load current conditions
do not cause excessive die temperatures. The following
formulas can be used as a rough guide to calculate LT1172
power dissipation. For more details, the reader is referred
to Application Note 19 (AN19), “Efficiency Calculations”
section.
Average supply current (including driver current) is:
I
IN
≈ 6mA + I
SW
(0.004 + DC/40)
I
SW
= switch current
DC = switch duty cycle
Switch power dissipation is given by:
P
SW
= (I
SW
)
2
• (R
SW
)(DC)
R
SW
= LT1172 switch “on” resistance (1Ω maximum)
Total power dissipation is the sum of supply current times
input voltage plus switch power:
P
D(TOT)
= (I
IN
)(V
IN
) + P
SW
In a typical example, using a boost converter to generate
12V at 0.12A from a 5V input, duty cycle is approximately
60%, and switch current is about 0.65A, yielding:
I
IN
= 6mA + 0.65(0.004 + DC/40) = 18mA
P
SW
= (0.65)
2
• (1Ω)(0.6) = 0.25W
P
D(TOT)
= (5V)(0.018A) + 0.25 = 0.34W
Temperature rise in a plastic miniDIP would be 130°C/W
times 0.34W, or approximately 44°C. The maximum ambi
-
ent temperature would be limited to 100°C (commercial
temperature limit) minus 44°C, or 56°C.
In most applications, full load current is used to calculate
die temperature. However, if overload conditions must
also be accounted for, four approaches are possible. First,
if loss of regulated output is acceptable under overload
conditions, the internal thermal limit of the LT1172 will
protect the die in most applications by shutting off switch
current. Thermal limit is not a tested parameter, however,
and should be considered only for noncritical applications
with temporary overloads. A second approach is to use the
larger TO-220 (T) or TO-3 (K) package which, even without
a heat sink, may limit die temperatures to safe levels under
overload conditions. In critical situations, heat sinking of
these packages is required; especially if overload conditions
must be tolerated for extended periods of time.
The third approach for lower current applications is to
leave the second switch emitter (miniDIP only) open. This
increases switch “on” resistance by 2:1, but reduces switch
current limit by 2:1 also, resulting in a net 2:1 reduction in
I
2
R switch dissipation under current limit conditions.
The fourth approach is to clamp the V
C
pin to a voltage
less than its internal clamp level of 2V. The LT1172 switch
current limit is zero at approximately 1V on the V
C
pin
and 2A at 2V on the V
C
pin. Peak switch current can be
externally clamped between these two levels with a diode.
See AN19 for details.
LT1170/LT1171/LT1172 Synchronizing
The LT1170/LT1171/LT1172 can be externally synchro
-
nized in the frequency range of 120kHz to 160kHz. This
is accomplished as shown in the accompanying figures.
Synchronizing occurs when the V
C
pin is pulled to ground
with an external transistor. To avoid disturbing the DC
characteristics of the internal error amplifier, the width of
the synchronizing pulse should be under 0.3µs. C2 sets
the pulse width at ≅ 0.2µs. The effect of a synchronizing
pulse on the LT1170/LT1171/LT1172 amplifier offset can
be calculated from:
ΔV
OS
=
KT
q
⎛
⎝
⎜
⎞
⎠
⎟
t
S
(
)
f
S
(
)
I
C
+
V
C
R3
⎛
⎝
⎜
⎞
⎠
⎟
I
C
KT
q
= 26mV at 25°C
t
C
= pulse width
f
S
= pulse frequency
I
C
= V
C
source current (≈200µA)
V
C
= operating V
C
voltage (1V to 2V)
R3 = resistor used to set mid-frequency “zero” in
frequency compensation network.
