CY28346
Document #: 38-07331 Rev. *C Page 14 of 20
Maximum Ratings
[5]
Input Voltage Relative to V
SS
:.............................. V
SS
– 0.3V
Input Voltage Relative to V
DDQ
or AV
DD
: ............. V
DD
+ 0.3V
Storage Temperature:................................ –65°C to + 150°C
Operating Temperature:.................................... 0°C to +85°C
Maximum Power Supply:................................................ 3.5V
Current Accuracy
[6]
Parameter Conditions Configuration Load Min. Max.
Iout V
DD
= nominal (3.30V) M0 = 0 or 1 and Rr (see Table 1) Nominal test load for given
configuration
–7%
Inom
+ 7%
Inom
Iout V
DD
= 3.30 ± 5% All combinations of M0 or 1 and Rr
(see Table 1)
Nominal test load for given
configuration
–12%
Inom
+ 12%
Inom
DC Parameters (V
DD
= V
DDA
= 3.3V ±5%, TA = 0°C to +70°C)
Parameter Description Conditions Min. Typ. Max. Unit
I
DD
3.3V Dynamic Supply Current All frequencies at maximum values
[7]
280 mA
I
PD
3.3V Power-down Supply Current PD# asserted Note 8 mA
C
IN
Input Pin Capacitance 5pF
C
OUT
Output Pin Capacitance 6pF
L
PIN
Pin Inductance 7nH
C
XTAL
Crystal Pin Capacitance Measured from the X
IN
or X
OUT
pin to ground 30 36 42 pF
AC Parameters (V
DD
= V
DDA
= 3.3V ±5%, T
A
= 0°C to +70°C)
Parameter Description
66 MHz 100 MHz 133 MHz 200 MHz
Unit NotesMin. Max. Min. Max. Min. Max. Min. Max.
Crystal
T
DC
X
IN
Duty Cycle 47.5 52.5 47.5 52.5 47.5 52.5 47.5 52.5 % 9, 10, 11
T
PERIOD
X
IN
period 69.84 71.0 69.84 71.0 69.84 71.0 69.84 71.0 ns 9, 12,
13, 10
V
HIGH
X
IN
HIGH Voltage 0.7V
DD
V
DD
0.7V
DD
V
DD
0.7V
DD
V
DD
0.7V
DD
V
DD
V
V
LOW
X
IN
LOW Voltage 0 0.3V
DD
00.3V
DD
00.3V
DD
00.3V
DD
V
T
R
/ T
F
X
IN
Rise and Fall Times 10.0 10.0 10.0 10.0 ns 14
T
CCJ
X
IN
Cycle to Cycle Jitter 500 500 500 500 ps 12, 15,
10
CPU at 0.7V Timing
T
DC
CPUT and CPUC Duty
Cycle
45 55 45 55 45 55 45 55 % 15, 16,
19
T
PERIOD
CPUT and CPUC
Period
14.85 15.3 9.85 10.2 7.35 7.65 4.85 5.1 ns 15, 16,
19
T
SKEW
Any CPU to CPU Clock
Skew
100 100 100 100 ps 12, 15,
16
Notes:
5. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
6. Inom refers to the expected current based on the configuration of the device.
7. All outputs loaded as per maximum capacitive load table.
8. Absolute value = ((Programmed CPU Iref) × (2)) + 10 mA.
9. This parameter is measured as an average over 1 µs duration, with a crystal center frequency of 14.31818 MHz.
10. When Xin is driven from an external clock source.
11. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock
duty cycle will not be within data sheet specifications.
12. All outputs loaded as perTable 9 below.
13. Probes are placed on the pins and measurements are acquired at 1.5V for 3.3V signals (see test and measurement set-up section of this data sheet).
14. Measured between 0.2V
DD
and 0.7V
DD
.
15. This measurement is applicable with Spread ON or Spread OFF.
16. Measured at crossing point (Vx) or where subtraction of CLK–CLK# crosses 0V Measured from V
OL
= 0.175V to V
OH
= 0.525V.
17. Measured from V
OL
= 0.175V to V
OH
= 0.525V.
18. Determined as a fraction of 2*(Trise–Tfall)/ (Trise+Tfall).
19. Test load is Rta = 33.2Ω, Rd = 49.9Ω.
